To tell the story of Interconnect, we must go back in time to the printed circuit board (PCB) test industry prior to the year 1990. At that time, electronics manufacturers relied upon a hands-on approach to test PCBs for structural integrity.
Our upcoming webinar, to be held on Tuesday, August 31st, 2021 at 10:30am Central Time and presented by ASSET's Michael R. Johnson, will describe the Component Action methodology, provide an in-depth view of the programming model, and demonstrate examples on a live target.
Since its inception, ScanWorks has provided board-level shorts and opens testing of interconnects between Boundary-Scan devices through use of its Automatic Test Pattern Generation (ATPG) feature. ScanWorks ATPG creates the patterns necessary for shorts and opens testing based on the board topology (i.e. connections between devices) and the Boundary-Scan Cell types on the I/O pins within each device. With recent enhancements, ScanWorks can now generate patterns that can be applied by chip-level automatic test equipment (ATE) to test for shorts and opens in the interconnections between silicon “chiplets” in multi-die devices.
Today, February 15th, 2020, marks the official 30th Anniversary of JTAG. What a wild ride it has been – from its humble beginnings for detecting short and open circuits, it has evolved to be, in some ways, the most powerful and feared technology on the planet. How did we get here?
JTAG is coming up on its 30th anniversary. And some would say it’s older than that. As I prepared for doing an introductory presentation on this amazing technology, I got a chance to reflect on how useful it has become, and what the next 30 years might be like.