Embedding JTAG into a system’s service processor allows for powerful out-of-band (independent of the operating system) built-in self test (BIST) functions. Using JTAG-based boundary scan, for example, can isolate system failure root cause to an extent unachievable through any other means.
High-end, mission-critical systems often use a plethora of diagnostic routines for power-on self test (POST), data logging, operational measurements, Built-In Self Test (BIST), and platform audits. Embedded x86 JTAG run-control adds out-of-band services to this mix. This article describes one such use case for Power-On Self Test (POST) of PCI Express ports.
In my last article, I described how the Open Compute Project (OCP) Project Olympus server designs have been put into the public domain by Microsoft Azure. Inherent in the Olympus servers is the hardware connection between the ASPEED BMC and the CPU JTAG chain. To make the most of this connection for hardware-assisted debug and test purposes, a high-performance, secure JTAG Master function is needed within the BMC.
As part of the Open Compute Project, Microsoft Azure is leading the charge in providing the technical information needed to democratize the server industry. Recently, they put into the public domain the full schematics and board files for an Intel Xeon Scalable Processor (Skylake-EP) server design. Reviewing the schematics provides great insight into the hardware design implementation needed to support at-scale debug via embedded JTAG run-control.
Last week, I suspected that I might be seeing segmentation fault failures on my new AMD Ryzen 7 1700X computer. I dug into this some more this week, and learned a lot!
I was up in Chicago last week, attending the IEEE-sponsored AUTOTESTCON conference. ASSET demonstrated our ScanWorks boundary-scan test support of the Teradyne High-Speed Subsystem (HSSub).
