Boundary Scan Archives | Page 5 of 11

JTAG and IJTAG-based Fast Flash Programming Algorithms

Alan Sguigna

March 20, 2016
5:11 pm

In recent years, the increasing size of flash memory has driven device programming to offline methods. However, new techniques are significantly reducing in-system programming times, making it much more feasible and convenient to program flash memory after it’s already been soldered to the board.

High Availability within Software-Defined Networks

Alan Sguigna

September 27, 2015
5:48 pm

As network functions become virtualized and proprietary hardware migrates to commodity Intel-based servers, will Carrier service levels degrade?

JTAG|DDR4 Connectivity Test Mode (JESD79-4)

Kent Zetterberg

September 22, 2015
2:45 pm

Recently launched DDR4 devices have what memory device vendors may refer to as a “boundary scan” test mode. Even though there’s not really a boundary-scan function involved on the DDR4 side, this mode actually has been, as claimed by JEDEC, “designed to work seamlessly with any boundary-scan devices.” Here’s a brief introduction to what it does and how to test it with a boundary-scan (JTAG) tool.

JTAG Boundary-Scan Test for the Intel Innovation Engine

Alan Sguigna

September 13, 2015
3:23 pm

As described in earlier blogs, the new Intel Innovation Engine (IE) makes an ideal host for validation, debug, trace and test applications on Intel platforms. This article details the implementation of a JTAG execution engine on the IE for the purposes of printed circuit board structural and functional testing.

Using the Intel Innovation Engine for Embedded DDR4 Memory Test

Alan Sguigna

September 7, 2015
3:28 pm

Last week, I wrote about Intel’s public announcement of the Innovation Engine (IE), an Intel architecture processor and I/O sub-system embedded into their upcoming generations of server platforms. This article describes the use of the IE for JTAG boundary-scan testing of memories.

Embedded Boundary-Scan Test

Alan Sguigna

August 2, 2015
6:09 pm

Boundary-scan test is used commonly on manufacturing lines with a “benchtop” tester, complete with cables, fixturing, hardware probes, and so on. What are the pros and cons of embedding this technology in-situ?