Boundary Scan Archives | Page 5 of 13

Master DDR3 tuning on Zynq-7000 with less technical reference manual (TRM) stress

Larry Osborn

August 14, 2018
2:45 pm

PFx support for the NXP SABRE Lite design for rapid startup

Larry Osborn

June 26, 2018
10:22 am

Rapid deployment for Xilinx Zynq-7000 just got a little easier

Larry Osborn

June 21, 2018
8:20 am

New embedded test technology enables improved DDR and IO testing plus fast flash programming

Larry Osborn

June 13, 2018
12:17 pm

Embedded JTAG for Built-In Self Test

Alan Sguigna

April 8, 2018
9:01 pm

Embedding JTAG into a system’s service processor allows for powerful out-of-band (independent of the operating system) built-in self test (BIST) functions. Using JTAG-based boundary scan, for example, can isolate system failure root cause to an extent unachievable through any other means.

Embedded Run-Control for Power-On Self Test

Alan Sguigna

March 18, 2018
5:07 pm

High-end, mission-critical systems often use a plethora of diagnostic routines for power-on self test (POST), data logging, operational measurements, Built-In Self Test (BIST), and platform audits. Embedded x86 JTAG run-control adds out-of-band services to this mix. This article describes one such use case for Power-On Self Test (POST) of PCI Express ports.

Boundary-Scan Test Using ScanWorks with Teradyne’s High Speed Subsystem

Michael Johnson

January 24, 2018
9:20 am

JTAG Master function for embedded debug and test

Alan Sguigna

December 10, 2017
4:49 pm

In my last article, I described how the Open Compute Project (OCP) Project Olympus server designs have been put into the public domain by Microsoft Azure. Inherent in the Olympus servers is the hardware connection between the ASPEED BMC and the CPU JTAG chain. To make the most of this connection for hardware-assisted debug and test purposes, a high-performance, secure JTAG Master function is needed within the BMC.

Microsoft Project Olympus Schematics and Embedded JTAG Run-Control

Alan Sguigna

December 3, 2017
4:26 pm

As part of the Open Compute Project, Microsoft Azure is leading the charge in providing the technical information needed to democratize the server industry. Recently, they put into the public domain the full schematics and board files for an Intel Xeon Scalable Processor (Skylake-EP) server design. Reviewing the schematics provides great insight into the hardware design implementation needed to support at-scale debug via embedded JTAG run-control.

The MinnowBoard Chronicles Episode 27: Segfault on my AMD Ryzen 7 1700X

Alan Sguigna

October 29, 2017
5:54 pm

Last week, I suspected that I might be seeing segmentation fault failures on my new AMD Ryzen 7 1700X computer. I dug into this some more this week, and learned a lot!

Category: Boundary Scan

Master DDR3 tuning on Zynq-7000 with less technical reference manual (TRM) stress

PFx support for the NXP SABRE Lite design for rapid startup

Rapid deployment for Xilinx Zynq-7000 just got a little easier

New embedded test technology enables improved DDR and IO testing plus fast flash programming

Embedded JTAG for Built-In Self Test

Embedded Run-Control for Power-On Self Test

Boundary-Scan Test Using ScanWorks with Teradyne’s High Speed Subsystem

JTAG Master function for embedded debug and test

Microsoft Project Olympus Schematics and Embedded JTAG Run-Control

The MinnowBoard Chronicles Episode 27: Segfault on my AMD Ryzen 7 1700X

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