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Why Healthcare Engineering Teams Are Reconsidering PCB Testing Outsourcing

ASSET InterTech

July 11, 2025
8:49 am

While outsourcing has long been a standard practice, many engineering teams are rethinking this strategy due to rising costs, time delays, and quality control issues. This article explores the key challenges of outsourcing PCB testing and introduces ScanWorks as a powerful in-house alternative.

How FPGAs Are Powering the Next Generation of Medical Devices and Diagnostics

ASSET InterTech

July 11, 2025
8:46 am

Engineering teams are under pressure to deliver smarter, faster, and more adaptable solutions. At the heart of this transformation is the Field-Programmable Gate Array (FPGA)—a reconfigurable hardware platform that’s redefining what’s possible in medical diagnostics and device design. In this article, we explore how FPGAs are reshaping the healthcare landscape.

Combining ASSET Fast Flash Programming Technology with Customer IP – Part 2: Integrating ScanWorks-Generated Instruments into Customer IP

John Akin

July 8, 2025
1:08 pm

In this blog we’re exploring how the FFP IP generated by ETG can be instantiated inside a customer-owned top-level design—empowering FPGA developers to bring high-performance flash programming into an already-optimized and verified HDL framework.

AI analysis of Intel Processor Trace from ENABLEJTAGBREAK to Windows’ first SMI

Alan Sguigna

June 15, 2025
5:15 pm

It is possible to break at the earliest part of Windows boot via the ENABLEJTAGBREAK facility made available within bootmgfw!BlBdWaitForJtagHwDebugger. In this article, there’s a short description and video whereby I’ve collected Intel Processor Trace as the target boots from early Windows to the first SMM entry; and then used AI to analyze it. The results are outstanding.

Using JTAG for Interrupt Handler Research

Alan Sguigna

May 26, 2025
1:33 pm

JTAG can be used to explore the behavior of interrupt dispatching internals in a new way. This article describes the functionality of the Interrupt Descriptor Table (IDT) as an Intel target is booted from the reset vector, through UEFI, and into Windows.

Using LLMs to analyze Hyper-V Register State and Instruction Trace

Alan Sguigna

May 11, 2025
4:24 pm

SourcePoint+AI is a new enhancement of the renowned JTAG-based debugger, which can reduce months' worth of analysis into minutes. For debugging and reverse engineering, it's like going from hunting with a stone spear to using a guided missile.

Using ChatGPT on Windows Secure Kernel with Intel Architectural Event Trace

Alan Sguigna

April 13, 2025
3:04 pm

This article describes the process of feeding ChatGPT with Intel Architectural Event Trace (AET) data generated during Windows secure boot.

Using ChatGPT on Windows Secure Kernel with Intel Processor Trace

Alan Sguigna

April 5, 2025
3:27 pm

In this article, the ChatGPT OpenAI LLM is used to provide insight into Windows instruction execution during a Secure Kernel to Normal Kernel transition.

Unlocking the Power of ScanWorks Fast Flash: Integrating Customer IP into FPGA Configurations – Part 1

John Akin

March 31, 2025
1:23 pm

In this blog post ASSET's John Akin explores integrating customer IP into FPGA configurations, and he dives into the innovative ways you can leverage ScanWorks Fast Flash Programming (FFP) technology to enhance your FPGA configurations.

The Mysterious Behavior of the Intel E-cores

Alan Sguigna

March 23, 2025
10:03 am

While doing some low-level debugging using SourcePoint, I noticed some interesting and puzzling behavior of Intel E-cores (based upon Atom architecture) versus P-cores (based on Core architecture).

Why Healthcare Engineering Teams Are Reconsidering PCB Testing Outsourcing

How FPGAs Are Powering the Next Generation of Medical Devices and Diagnostics

Combining ASSET Fast Flash Programming Technology with Customer IP – Part 2: Integrating ScanWorks-Generated Instruments into Customer IP

AI analysis of Intel Processor Trace from ENABLEJTAGBREAK to Windows’ first SMI

Using JTAG for Interrupt Handler Research

Using LLMs to analyze Hyper-V Register State and Instruction Trace

Using ChatGPT on Windows Secure Kernel with Intel Architectural Event Trace

Using ChatGPT on Windows Secure Kernel with Intel Processor Trace

Unlocking the Power of ScanWorks Fast Flash: Integrating Customer IP into FPGA Configurations – Part 1

The Mysterious Behavior of the Intel E-cores

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