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In my last few blogs, I’ve looked at the use of Intel Trace features for capturing valuable debug information. In particular, Architectural Event Trace (AET) and Management Engine (ME) message trace are very powerful capabilities. This week, we put these trace events in a meaningful code context by correlating them with Intel Processor Trace (IPT).
Last week, I used Architectural Event Trace (AET) to capture all events that invoked Model Specific Register (MSR) reads and writes. This week, I use the Trace Hub to trace Intel Management Engine (ME, also known as Converged Security and Management Engine (CSME)) events.
Last week, I wrote an introduction to Architectural Event Trace, an extremely powerful JTAG-based Trace facility within current Intel silicon. Using this technology in conjunction with SourcePoint gives the firmware developer unprecedented insight into program execution and events. This week, I look at some of the use cases.
Yes, Intel Skylake-EP, also known as Skylake-SP, or Purley, or Intel Xeon Scalable Processor, is past the “line of demarcation”; which means some more of its powerful capabilities can be revealed in the public domain. I managed to get my hands on a server platform with this CPU, and looked at some of the advanced debug and trace capabilities within the silicon.
Today, February 15th, 2020, marks the official 30th Anniversary of JTAG. What a wild ride it has been – from its humble beginnings for detecting short and open circuits, it has evolved to be, in some ways, the most powerful and feared technology on the planet. How did we get here?
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