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Intel Processor Trace and AET

Alan Sguigna

April 5, 2020
5:16 pm

In my last few blogs, I’ve looked at the use of Intel Trace features for capturing valuable debug information. In particular, Architectural Event Trace (AET) and Management Engine (ME) message trace are very powerful capabilities. This week, we put these trace events in a meaningful code context by correlating them with Intel Processor Trace (IPT).

Intel Management Engine (ME) Event Trace

Alan Sguigna

March 29, 2020
4:49 pm

Last week, I used Architectural Event Trace (AET) to capture all events that invoked Model Specific Register (MSR) reads and writes. This week, I use the Trace Hub to trace Intel Management Engine (ME, also known as Converged Security and Management Engine (CSME)) events.

Advanced Capabilities of Architectural Event Trace

Alan Sguigna

March 22, 2020
5:23 pm

In the first and second episodes of this series, I did a basic introduction of how to set up AET and to trace I/O reads and writes. This week, I look at tracing all Model Specific Register (MSR) reads and writes.

Intel Architectural Event Trace (AET) in action

Alan Sguigna

March 15, 2020
9:31 pm

Last week, I wrote an introduction to Architectural Event Trace, an extremely powerful JTAG-based Trace facility within current Intel silicon. Using this technology in conjunction with SourcePoint gives the firmware developer unprecedented insight into program execution and events. This week, I look at some of the use cases.

Intel Architectural Event Trace (AET)

Alan Sguigna

March 8, 2020
2:57 pm

Yes, Intel Skylake-EP, also known as Skylake-SP, or Purley, or Intel Xeon Scalable Processor, is past the “line of demarcation”; which means some more of its powerful capabilities can be revealed in the public domain. I managed to get my hands on a server platform with this CPU, and looked at some of the advanced debug and trace capabilities within the silicon.

It’s JTAG’s 30th Anniversary!

Alan Sguigna

February 15, 2020
3:29 pm

Today, February 15th, 2020, marks the official 30th Anniversary of JTAG. What a wild ride it has been – from its humble beginnings for detecting short and open circuits, it has evolved to be, in some ways, the most powerful and feared technology on the planet. How did we get here?

Board Bring-Up of the i.MX6 Saber Lite

Alan Sguigna

January 26, 2020
3:47 pm

I received a bricked Saber Lite board as a gift. Before I could do anything useful with it, I had to get it to boot.

Benchmarking Yocto OpenBMC Builds Part 3: Ampere Computing on Packet

Alan Sguigna

January 12, 2020
5:40 pm

In Part 1, I compared the performance and cost of Intel Cascade Lake versus AMD Rome. In Part 2, I compared these against Amazon’s own Graviton1 CPU. In this article, I benchmarked Ampere Computing’s eMAG, available on Packet.com.

Benchmarking Yocto OpenBMC Builds on AWS Part 2: Arm64, Intel and AMD

Alan Sguigna

January 5, 2020
12:41 pm

In Part 1, I compared the performance and cost of Intel Cascade Lake versus AMD Rome. How does Amazon’s own CPU, Graviton, fare in this benchmark?

Benchmarking Yocto OpenBMC Builds on AWS Part 1: Intel Cascade Lake versus AMD Rome

Alan Sguigna

December 26, 2019
4:39 pm

As you know, I’ve done a lot of OpenBMC builds on my AMD Ryzen desktop PC, as well as my Surface Pro 6. I decided to tackle the same builds on Amazon Web Services (AWS), on virtual machines based on the Intel Cascade Lake CPU, as well as the AMD EPYC 7000. Which one is faster and cheaper?

Intel Processor Trace and AET

Intel Management Engine (ME) Event Trace

Advanced Capabilities of Architectural Event Trace

Intel Architectural Event Trace (AET) in action

Intel Architectural Event Trace (AET)

It’s JTAG’s 30th Anniversary!

Board Bring-Up of the i.MX6 Saber Lite

Benchmarking Yocto OpenBMC Builds Part 3: Ampere Computing on Packet

Benchmarking Yocto OpenBMC Builds on AWS Part 2: Arm64, Intel and AMD

Benchmarking Yocto OpenBMC Builds on AWS Part 1: Intel Cascade Lake versus AMD Rome

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