IJTAG Archives | ASSET InterTech

IEEE 1687 (IJTAG): ICL and PDL Explained

Alan Sguigna

February 26, 2023
1:40 pm

With IEEE 1687 (aka IJTAG) making its way into a great many chips as a mainstream mechanism for access and control of embedded instrumentation, I’ve taken an interest in explaining this often complicated technology in simple terms. I’ll start with describing the syntax, semantics and overall structure of Instrument Connectivity Language (ICL) and Procedural Description Language (PDL).

The IEEE 1149.1-2013 Standard for Test Access Port and Boundary-Scan Architecture: An Overview

Alan Sguigna

December 18, 2022
3:58 pm

An overview of some of the technology behind the IEEE 1149.1-2013 Revision.

US Government playing Football with Semiconductor Market?

Glenn Woppman

October 20, 2022
6:06 pm

As most of us know, football season began across America last month, with both college and the NFL seasons starting. With the recent moves by our Federal Government, it seems they have a bit of a football game strategy when it comes to the semiconductor market segment.

Semiconductor Test: What opportunities are created by passing the CHIPS bill?

Glenn Woppman

August 29, 2022
1:17 pm

The CHIPS Act as a byproduct will create a fantastic opportunity for high-paying semiconductor test, design-for-test and validation engineering jobs for America.

What are Chipkits?

Alan Sguigna

August 22, 2022
8:12 am

Cyber attackers use Rootkits to implant malware using Operating System internals. Bootkits are for more persistent implants, targeted toward UEFI firmware vulnerabilities. But, what if you go lower down, into the silicon? This is a Chipkit.

Video recording of Chiplet interconnect test webinar

Alan Sguigna

December 3, 2020
5:14 pm

In case you missed it, a recording of Michael Johnson's webinar, Chiplet Interconnect Testing using JTAG/Boundary Scan, is now available. Click on the link, and enjoy the show.

It’s JTAG’s 30th Anniversary!

Alan Sguigna

February 15, 2020
3:29 pm

Today, February 15th, 2020, marks the official 30th Anniversary of JTAG. What a wild ride it has been – from its humble beginnings for detecting short and open circuits, it has evolved to be, in some ways, the most powerful and feared technology on the planet. How did we get here?

Using JTAG for Silicon Trojan Detection and Mitigation

Alan Sguigna

September 1, 2019
11:53 am

This past week, I attended the AUTOTESTCON 2019 conference, the premiere Defense Automated Test Equipment show, that has the theme of “increased mission effectiveness through advanced test and support technology”. As you may have seen, I was honored with the “Walter E. Peterson Best Paper on New Technology” award for Mitigating JTAG as an Attack Surface (note: it might take a little while for the paper to be posted on IEEE Xplore; you might have to check back later).

Locks, Keys and Traps: Securing device JTAG interfaces

Alan Sguigna

July 10, 2017
5:57 pm

In two previous articles, I looked at the JTAG access port from a security perspective, and considered what exposure the choice of BMC operating system might have on a platform supporting At-Scale Debug. Now, let’s consider the root of all trust, the silicon itself, and see what options exist for locking it down.

Security of BMC Operating Systems

Alan Sguigna

July 2, 2017
1:58 pm

Given that they are network-accessible, BMCs present an attack surface. Which operating systems are hardened enough to be secure against malicious actors?

Category: IJTAG

IEEE 1687 (IJTAG): ICL and PDL Explained

The IEEE 1149.1-2013 Standard for Test Access Port and Boundary-Scan Architecture: An Overview

US Government playing Football with Semiconductor Market?

Semiconductor Test: What opportunities are created by passing the CHIPS bill?

What are Chipkits?

Video recording of Chiplet interconnect test webinar

It’s JTAG’s 30th Anniversary!

Using JTAG for Silicon Trojan Detection and Mitigation

Locks, Keys and Traps: Securing device JTAG interfaces

Security of BMC Operating Systems

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