FPGA-Controlled Test (FCT) Archives

The Basys Chronicles Episode 3: Flashing the Quad SPI

Alan Sguigna

November 17, 2019
4:59 pm

In Episode 2 of the Basys Chronicles, I configured (programmed) the Artix-7 FPGA with a simple Binary-to-Decimal calculator application, through the USB-JTAG port. But, power down the Basys 3, and it goes back to the Built-In Self Test that comes with the board. This week, I flashed the calculator configuration into the nonvolatile SPI flash, making it the default boot-up configuration.

The Basys Chronicles Episode 2: A Simple Binary-to-Decimal Calculator

Alan Sguigna

November 11, 2019
7:38 pm

In the Basys Chronicles Episode 1, I started to learn about FPGA programming using Xilinx’s Vivado tool and the Digilent Basys 3 Trainer Board. Now, after a few weeks (okay, time flies; it’s been almost two months), I’ve made some good headway in understanding FPGA architecture and creating some interesting designs that do useful things.

The Basys Chronicles Episode 1: A Newbie’s Approach to Learning FPGA Programming

Alan Sguigna

September 15, 2019
7:57 pm

I don’t know why, but I woke up a few weeks ago with an urge to teach myself FPGA programming. Here’s how I went about it.

ASSET exhibits at the AUTOTESTCON Conference

Alan Sguigna

September 19, 2017
7:38 am

I was up in Chicago last week, attending the IEEE-sponsored AUTOTESTCON conference. ASSET demonstrated our ScanWorks boundary-scan test support of the Teradyne High-Speed Subsystem (HSSub).

Advanced support for Teradyne HSSub PXIe systems

Alan Sguigna

September 11, 2017
7:48 am

We announced today the extended integration of ScanWorks’ boundary-scan test capabilities with the Teradyne’s PXI Express-based High Speed Subsystem (HSSub). Come see a demo at Booth #101 at the AUTOTESTCON conference!

ASSET and CCI collaborate on integrated test solutions

Alan Sguigna

January 17, 2017
8:10 pm

Combining boundary-scan structural test with functional test is a “best practice” approach to high test coverage at least cost. So, it only makes sense that ASSET collaborates with Circuit Check.

NBT at the BTW

Alan Sguigna

September 18, 2016
4:12 pm

ASSET’s Michael Johnson presented an update on Non-intrusive Board Test (NBT) at the 13th Annual Board Test Workshop (BTW) in Fort Collins, CO this past week. The overall question posed at the Workshop was, “Is Board Test Losing Relevance”?

JTAG and IJTAG-based Fast Flash Programming Algorithms

Alan Sguigna

March 20, 2016
5:11 pm

In recent years, the increasing size of flash memory has driven device programming to offline methods. However, new techniques are significantly reducing in-system programming times, making it much more feasible and convenient to program flash memory after it’s already been soldered to the board.

JTAG Boundary-Scan Test for the Intel Innovation Engine

Alan Sguigna

September 13, 2015
3:23 pm

As described in earlier blogs, the new Intel Innovation Engine (IE) makes an ideal host for validation, debug, trace and test applications on Intel platforms. This article details the implementation of a JTAG execution engine on the IE for the purposes of printed circuit board structural and functional testing.

Faster Flash Programming via FPGA and IJTAG

Alan Sguigna

July 14, 2015
11:59 am

Category: FPGA-Controlled Test (FCT)

The Basys Chronicles Episode 3: Flashing the Quad SPI

The Basys Chronicles Episode 2: A Simple Binary-to-Decimal Calculator

The Basys Chronicles Episode 1: A Newbie’s Approach to Learning FPGA Programming

ASSET exhibits at the AUTOTESTCON Conference

Advanced support for Teradyne HSSub PXIe systems

ASSET and CCI collaborate on integrated test solutions

NBT at the BTW

JTAG and IJTAG-based Fast Flash Programming Algorithms

JTAG Boundary-Scan Test for the Intel Innovation Engine

Faster Flash Programming via FPGA and IJTAG

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