Arium Probes | SourcePoint™ Archives

Webinar: Intel Architectural Event Trace

Alan Sguigna

February 23, 2021
2:16 pm

Don't miss it! ASSET's Alan Sguigna (that's me), in collaboration with the UEFI Forum, will be presenting and demonstrating SourcePoint using the Intel Architectural Event Trace (AET) feature, which offers an unparalleled level of insight into x86 event generation and code execution.

Webinar: JTAG-based debugging of AMD EPYC servers

Alan Sguigna

January 5, 2021
6:09 pm

ASSET is pleased to announce that yours truly is presenting a technical session on JTAG-based firmware debugging of AMD EPYC servers, to be held on Wednesday, January 27th at 1:30pm Central Standard Time.

The UP Squared Chronicles Episode 4: Using Intel Processor Trace with POST Codes

Alan Sguigna

January 3, 2021
11:52 am

I became curious this past week on how UEFI handles POST codes. These are “markers” for the boot process, and tells you at what stage the platform initialization is. Can we easily correlate POST codes with the operation of the UEFI firmware?

The UP Squared Chronicles Episode 3: Intel Processor Trace

Alan Sguigna

December 21, 2020
8:31 am

Wow! It has been a while. I wrote Episode 2 of my open-source explorations into the AAEON Intel Apollo Lake-based Up Squared board back on June 7th. In that episode, I gave directions on how to build the UEFI debug image for the board, complete with source/symbols for consumption by JTAG debuggers like SourcePoint. In this episode, I show source-level debug with SourcePoint, and take advantage of Intel Processor Trace on the board.

Coding to the SED API: Part 1

Alan Sguigna

August 30, 2020
4:11 pm

In my UEFI Forum webinar, I demonstrated a utility function for stressing PCI Express ports at-scale using JTAG. Let’s walk through the source code and see how it works under the hood.

Debugging Intel CATERR using Embedded ITP

Alan Sguigna

July 26, 2020
8:44 pm

In my webinar with the UEFI Forum, I demonstrated some of the utility of using JTAG functionality within BMCs to perform out-of-band debug. This is a tutorial on the coding practices to use the SED API.

PCI Express LTSSM stress using BMC-based Embedded JTAG/ITP

Alan Sguigna

July 19, 2020
4:27 pm

This past week, I did a webinar in collaboration with the UEFI Forum on JTAG-based UEFI Debug and Trace. This reviewed some of the often-used tools for low-level triage of difficult-to-diagnose, intermittent bugs. Near the end, I demonstrated the usage of technology running directly down on a BMC to perform low-level functions not achievable with firmware or OS-based applications.

Webinar on JTAG-based UEFI Debug & Trace

Alan Sguigna

June 24, 2020
2:23 pm

ASSET will be presenting JTAG-based UEFI Debug & Trace at the UEFI Forum’s 2020 Virtual Plugfest, on July 14th.

The UP Squared Chronicles Episode 2: Building the UEFI Image

Alan Sguigna

June 7, 2020
5:55 pm

In Episode 1 of the UP Squared Chronicles, I used my DediProg SF100 to flash a debug image equipped with source and symbols onto the UP Squared board. This week, I describe the build process.

More Skylake Server CScripts Explorations

Alan Sguigna

May 31, 2020
1:18 pm

In Running Intel CScripts on Skylake servers, I gave a brief introduction to the Intel Customer Scripts (CScripts), and showed how to run them with SourcePoint. Today, I do a deeper dive.

Category: Arium Probes | SourcePoint™

Webinar: Intel Architectural Event Trace

Webinar: JTAG-based debugging of AMD EPYC servers

The UP Squared Chronicles Episode 4: Using Intel Processor Trace with POST Codes

The UP Squared Chronicles Episode 3: Intel Processor Trace

Coding to the SED API: Part 1

Debugging Intel CATERR using Embedded ITP

PCI Express LTSSM stress using BMC-based Embedded JTAG/ITP

Webinar on JTAG-based UEFI Debug & Trace

The UP Squared Chronicles Episode 2: Building the UEFI Image

More Skylake Server CScripts Explorations

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