It is often part of a hardware validation test suite to initiate multiple PCIe bus retrains, looking for hardware design issues, or LTSSM RTL bugs in the device under test. These test suites take a very long time to run. Is there a way to speed them up?
ASSET joined the Open Compute Project (OCP) earlier this year, and we attended our first Engineering Workshop in Dallas last week. The theme of this session was the OCP Telco Project. What did we learn?
When an x86 system has crashed, gathering forensics data to help diagnose root-cause of the failure is a top priority. But, how is this done if the system has crashed, and OS/BIOS-based application programs cannot access the platform?