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Category: Intel® IBIST

Single Stripline versus Dual Stripline, and Board Routing

Alan Sguigna
Alan Sguigna
  • 2:00 pm
In the previous blog on PCB Insertion Loss and High-Speed Buses, we described how this loss increases with greater link speed. Designing for higher link speeds may, as a consequence, drive up PCB cost. This blog explains some techniques to mitigate this cost increase.

PCB Insertion Loss and High-Speed Buses

Alan Sguigna
Alan Sguigna
  • 3:54 pm
As high-speed differential buses on today’s board designs become faster, the maximum allowable PCB insertion loss declines. What causes this effect, and how can it be mitigated?

DDR Crosstalk Analysis using Margining Technologies

Alan Sguigna
Alan Sguigna
  • 8:02 pm
In the article DDR4 Memory Timing Margining, we described more sophisticated DDR margining tests, which determine crosstalk coupling between aggressor channels, dwords (lanes 0-31), words, bytes and lanes. How can designers use these capabilities?

PCI Express 4.0, Retimers, and Trace Length

Alan Sguigna
Alan Sguigna
  • 4:39 pm
At their developers conference two weeks ago, PCI-SIG representatives talked about doubling the bandwidth of PCI Express 3.0, while still preserving channel runs of up to 20 inches, the length of the traditional server’s data path. How is this achieved?

Bit Error Rate of Intel QuickPath Interconnect – Part 2

Alan Sguigna
Alan Sguigna
  • 4:34 pm
In a previous blog, we touched on some of the key attributes of Intel QuickPath Interconnect versus PCI Express Gen3, to explain why the acceptable bit error rate threshold of Intel QPI is two orders of magnitude lower. This article elaborates on how some of the key design features of QPI contribute to this more stringent requirement.
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