In the previous blog on PCB Insertion Loss and High-Speed Buses, we described how this loss increases with greater link speed. Designing for higher link speeds may, as a consequence, drive up PCB cost. This blog explains some techniques to mitigate this cost increase.
In the article DDR4 Memory Timing Margining, we described more sophisticated DDR margining tests, which determine crosstalk coupling between aggressor channels, dwords (lanes 0-31), words, bytes and lanes. How can designers use these capabilities?
At their developers conference two weeks ago, PCI-SIG representatives talked about doubling the bandwidth of PCI Express 3.0, while still preserving channel runs of up to 20 inches, the length of the traditional server’s data path. How is this achieved?
In a previous blog, we touched on some of the key attributes of Intel QuickPath Interconnect versus PCI Express Gen3, to explain why the acceptable bit error rate threshold of Intel QPI is two orders of magnitude lower. This article elaborates on how some of the key design features of QPI contribute to this more stringent requirement.