Category: IJTAG

Brian Bailey, editor of EETimesโ€™ EDA Designline, recently penned a blog questioning the ubiquity and value of embedded instrumentation within chips. Itโ€™s a fascinating and timely read, and Iโ€™d like to put my two cents worth inโ€ฆ
Testing high-speed memories soldered to a circuit board is as elusive as it is critical for overall system performance. Testing DDR3 and DDR4 memory buses can be particularly tricky, given the fact that DDR is so fast and that the bus carries the clock and data on both the rising and falling edges of the signal. Sorting all of that out and making sure it stays sorted out over the life cycle of a system can be a daunting challenge.
Board bring-up is a phased process whereby an electronics system is repeatedly tested, validated and debugged, in order to achieve readiness for manufacture. This process can take so long that a product never gets to market because it is succeeded by the next generation...
Programming NOR or large NAND flash devices can be done using a variety of technologies, including boundary scan (JTAG), processor-controlled test (emulation), or FPGA-controlled test. Which embedded instrument you use is a trade-off between speed, complexity and cost.
I was reflecting on how much processor speeds, memory, and data transmission rates have increased over the last few decades. And yet the same old tools and techniques are often used to bring up new designs. When do you think we fall off the cliff?
One of the newest IEEE Standards Committees is currently defining the P1838 3D Test Standard. The main goal of P1838 is to develop a โ€œPer Dieโ€ Access Mechanism that becomes a โ€œStacked Dieโ€ Access Mechanism when the individual die are stacked into 3D silicon. Find out moreโ€ฆ
Board bring up of an early prototype is one of the most important steps for a design team. The first boards must pass through a battery of tests to demonstrate that the hardware is rock-solid. Non-intrusive technologies can be used to accelerate this process.
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