Programming NOR or large NAND flash devices can be done using a variety of technologies, including boundary scan (JTAG), processor-controlled test (emulation), or FPGA-controlled test (IJTAG). Which embedded instrument you use is a trade-off between speed, complexity and cost.
Programming non-volatile storage devices after they’ve been placed on a board has long been recognized as a good way to reduce the handling of the device. And, when this capability has been designed into the board itself, it also allows for updating of these memories in the field – a major plus for anything from iPhones to Blu-Ray players.
More recently, trends in the use of new phase-change memory (PCM) is forcing a much greater trend towards device programming post-reflow: https://blog.asset-intertech.com/test_data_out/2011/11/programming-devices-at-in-circuit-test.html.
Programming of flash memory in-situ is mostly conveniently done by taking advantage of the embedded instruments that already exist in commercial silicon. Let’s look at three examples:
JTAG is commonly used to program flash through the boundary registers of adjacent devices which have access to its address and data pins. The programming speed is constrained by the TCK of the slowest device in the chain, the number of boundary scan cells in the chain, and other factors. There are Design for Test (DFT) “tricks” that the engineer can use to speed up programming time, such as using a scan path linker to separate out slower TCK devices, providing access to the ready/busy and write enable pins, and using flash IP like the Firecron JTS15S to shorten the boundary scan register of the programming device. But, of the three technologies used to program flash, this is the slowest. For a design with a TCK chain speed of 2MHz and 400 or so cells in the main chain, it can take ten minutes or so to program a 512kB NOR flash; about 1kB per second.
Processor-controlled test (PCT) provides a faster method of programming flash than boundary scan, because it runs at the full system speed of the board’s main processor. And, PCT has a “fast flash programming” mode for certain processors that can get programming times down to 100kB per second. For more information, have a look at this link: http://www.asset-intertech.com/download/app9_fast_flash_programming.pdf.
In cases where NOR or NAND flash is hanging directly off an FPGA, FPGA-Controlled Test (FPGA) will be the most expedient, fastest and cheapest solution. FCT programming speeds can rival those of PCT, and involve downloading blocks of the flash binary image and programming algorithm into the host FPGA. This FPGA embedded instrument is used temporarily during board manufacturing or batch board upgrades, and is based upon an IEEE P1687 (IJTAG) access and control infrastructure: http://www.asset-intertech.com/pdfs/FPGA-Controlled_Test_white_paper.pdf.