Blog

Performance Counters for Malware Detection: a Survey

Alan Sguigna

July 18, 2021
4:09 pm

There have been numerous investigations into the use of the Performance Monitoring Counters (PMCs) for malware detection. Below is a quick survey of what I’ve read so far, as well as an investigation into using JTAG as an alternative access mechanism to traditional ring 0 or restricted OS mechanisms.

Webinar: Super-fast Flash Programming

Alan Sguigna

July 5, 2021
6:41 pm

100X faster than boundary scan! Watch this webinar recording of JTAG-based technologies used to do ultra-high-speed flash device programming.

Coding to the SED API: Part 5

Alan Sguigna

May 2, 2021
3:31 pm

In this installment of the Coding to the SED API series, we’ll look at the SED functions that access the OOBMSM, and use it for super-fast retrieval of hardware telemetry data.

Webinar: Embedded JTAG/boundary scan for Built-In Self Test

Alan Sguigna

April 25, 2021
12:20 pm

Attend our webinar on using JTAG as firmware for implementing boundary scan as Built-In Self Test.

The UP Squared Chronicles Episode 5: Installing and Debugging Windows 10

Alan Sguigna

April 25, 2021
12:09 pm

I hadn’t done anything with my Apollo Lake-based AAEON UP Squared board for a while. It was time to pull it down off the shelf, install Windows 10, and use SourcePoint to debug the platform.

A Trio of Webinars on x86 JTAG-based Debugging

Alan Sguigna

April 10, 2021
5:23 pm

For each of the months of January, February and March, I did a webinar on JTAG-based debugging. Since each of the video recordings are about 45 minutes long, I thought it would be helpful to point out the highlights of each, if you don’t have time to sit through the full durations. At the risk of sounding immodest, there are some real gems of information within the demos of each webinar.

Webinar: Embedded @Scale JTAG-based Debug of x86 Servers

Alan Sguigna

March 7, 2021
4:20 pm

Beginning with Microsoft Azure's Project Olympus, and now a standard within the Open Compute Project, many datacenter servers are now optionally equipped with hardware connectivity between the platform BMC and CPU scan chain. The BMC can thus act as an autonomous JTAG-based embedded out-of-band debug agent, provide low-level triage of system events, such as crashes and hangs. Other use cases, such as hardware validation, manufacturing test, and forensics telemetry are also enabled by this technology.

Webinar: Intel Architectural Event Trace

Alan Sguigna

February 23, 2021
2:16 pm

Don't miss it! ASSET's Alan Sguigna (that's me), in collaboration with the UEFI Forum, will be presenting and demonstrating SourcePoint using the Intel Architectural Event Trace (AET) feature, which offers an unparalleled level of insight into x86 event generation and code execution.

Webinar: JTAG-based debugging of AMD EPYC servers

Alan Sguigna

January 5, 2021
6:09 pm

ASSET is pleased to announce that yours truly is presenting a technical session on JTAG-based firmware debugging of AMD EPYC servers, to be held on Wednesday, January 27th at 1:30pm Central Standard Time.

The UP Squared Chronicles Episode 4: Using Intel Processor Trace with POST Codes

Alan Sguigna

January 3, 2021
11:52 am

I became curious this past week on how UEFI handles POST codes. These are “markers” for the boot process, and tells you at what stage the platform initialization is. Can we easily correlate POST codes with the operation of the UEFI firmware?

Performance Counters for Malware Detection: a Survey

Webinar: Super-fast Flash Programming

Coding to the SED API: Part 5

Webinar: Embedded JTAG/boundary scan for Built-In Self Test

The UP Squared Chronicles Episode 5: Installing and Debugging Windows 10

A Trio of Webinars on x86 JTAG-based Debugging

Webinar: Embedded @Scale JTAG-based Debug of x86 Servers

Webinar: Intel Architectural Event Trace

Webinar: JTAG-based debugging of AMD EPYC servers

The UP Squared Chronicles Episode 4: Using Intel Processor Trace with POST Codes

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