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Test Generation for “Chiplet”-based, Multi-die Devices Is Now Possible with ScanWorks

Michael Johnson
Michael Johnson
  • 1:28 pm
Since its inception, ScanWorks has provided board-level shorts and opens testing of interconnects between Boundary-Scan devices through use of its Automatic Test Pattern Generation (ATPG) feature. ScanWorks ATPG creates the patterns necessary for shorts and opens testing based on the board topology (i.e. connections between devices) and the Boundary-Scan Cell types on the I/O pins within each device. With recent enhancements, ScanWorks can now generate patterns that can be applied by chip-level automatic test equipment (ATE) to test for shorts and opens in the interconnections between silicon “chiplets” in multi-die devices.

More Skylake Server CScripts Explorations

Alan Sguigna
Alan Sguigna
  • 1:18 pm
In Running Intel CScripts on Skylake servers, I gave a brief introduction to the Intel Customer Scripts (CScripts), and showed how to run them with SourcePoint. Today, I do a deeper dive.

The MinnowBoard Chronicles Episode 46: Using the DediProg SF100

Alan Sguigna
Alan Sguigna
  • 3:04 pm
I’ve been working from home for quite some time now, and don’t have access to all the equipment I normally would have at the office. And I’ve wanted to flash the MinnowBoard (and some other boards). So, rather than wait for the coronavirus shelter-in-place to lift, I went out and bought a DediProg SF100 of my own. Here’s my out-of-the-box experience.

Running Intel CScripts on Skylake servers

Alan Sguigna
Alan Sguigna
  • 3:58 pm
As everyone who works with server designs knows, Intel publishes a group of JTAG-based scripts called the Intel Customer Scripts (ICS, or CScripts for short). The CScripts are derived from internal applications that Intel uses for silicon validation, and they are enormously useful for board bring-up and debug. This week, I took a look at them, and ran some with SourcePoint.

Intel Processor Trace and AET

Alan Sguigna
Alan Sguigna
  • 5:16 pm
In my last few blogs, I’ve looked at the use of Intel Trace features for capturing valuable debug information. In particular, Architectural Event Trace (AET) and Management Engine (ME) message trace are very powerful capabilities. This week, we put these trace events in a meaningful code context by correlating them with Intel Processor Trace (IPT).

Intel Management Engine (ME) Event Trace

Alan Sguigna
Alan Sguigna
  • 4:49 pm
Last week, I used Architectural Event Trace (AET) to capture all events that invoked Model Specific Register (MSR) reads and writes. This week, I use the Trace Hub to trace Intel Management Engine (ME, also known as Converged Security and Management Engine (CSME)) events.

Intel Architectural Event Trace (AET) in action

Alan Sguigna
Alan Sguigna
  • 9:31 pm
Last week, I wrote an introduction to Architectural Event Trace, an extremely powerful JTAG-based Trace facility within current Intel silicon. Using this technology in conjunction with SourcePoint gives the firmware developer unprecedented insight into program execution and events. This week, I look at some of the use cases.
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