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Boundary Scan Description Language (BSDL) provides a description of testability features within ICs that comply with the IEEE 1149.1 Standard (hereinafter used interchangeably with the term “JTAG”). Having a good understanding of the BSDL leads to a deeper knowledge of JTAG, that in turn grants insight into the technology behind IEEE 1687, also known as IJTAG.
With IEEE 1687 (aka IJTAG) making its way into a great many chips as a mainstream mechanism for access and control of embedded instrumentation, I’ve taken an interest in explaining this often complicated technology in simple terms. I’ll start with describing the syntax, semantics and overall structure of Instrument Connectivity Language (ICL) and Procedural Description Language (PDL).
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