It’s been great to reconnect with our Boundary Scan customers across the United States and Europe over the last several months discussing the new and exciting projects they have in the works. It’s also exciting to learn how our Boundary Scan product, ScanWorks, will play an integral role in the test, debug, validation, and deployment of these products. During one of these recent visits to a company that I consider a real power user of ScanWorks, the engineering manager who was participating in the meeting asked, “What is the best way for our new engineers to learn Boundary Scan?”
Currently with all the CHIPS Acts that have passed globally, the semiconductor industry has the money flowing; now we need to find and grow all the technical talent. An article just published (Taipei Times, July 26) based on a study by the Semiconductor Industry Association (SIA) and Oxford Economics states the US could be short 67,000 chip workers by 2030. Per the report, the US chip industry will grow to 460,000 workers, up from 340,000 today. Great news in terms of jobs and opportunities, but where will the technical talent come from is the next challenge.
In addition to the BC_1 Boundary Scan cell type, there are more Boundary Scan cell types that can be used to create a Boundary Scan Register and implement the IEEE 1149.1 operations within a Boundary Scan device. The type(s) of Boundary Scan cell(s) implemented within a device are listed in the BSDL. Basic Cell (BC)_0 through BC_7 are the standard Boundary Scan cell types commonly found in an IEEE 1149.1 compliant Boundary Scan device. You may ask the question, “Are there more Boundary Scan cells than BC_0 through BC_7?”
Boundary Scan Description Language (BSDL) provides a description of testability features within ICs that comply with the IEEE 1149.1 Standard (hereinafter used interchangeably with the term “JTAG”). Having a good understanding of the BSDL leads to a deeper knowledge of JTAG, that in turn grants insight into the technology behind IEEE 1687, also known as IJTAG.