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Using the Intel Trace Hub for at-speed printf

Alan Sguigna

September 6, 2021
5:27 pm

For debugging firmware, print statements (“printf”) are often our most powerful tool: some bugs are caused by complex sequences of events that are too long and intricate to root-cause using just breakpoints and watch windows. In this article, I write about my explorations into “at-speed printf”.

JTAG-based debug of AMD servers: webinar notes

Alan Sguigna

August 22, 2021
3:40 pm

Earlier this year, I did a webinar on using our SourcePoint JTAG-based debugger on AMD EPYC platforms. Below is the transcript of the audio, for those who prefer to read some of the material.

[Webinar] Squeezing out more test coverage with Component Action

Alan Sguigna

August 1, 2021
3:56 pm

Our upcoming webinar, to be held on Tuesday, August 31st, 2021 at 10:30am Central Time and presented by ASSET's Michael R. Johnson, will describe the Component Action methodology, provide an in-depth view of the programming model, and demonstrate examples on a live target.

Performance Counters for Malware Detection: a Survey

Alan Sguigna

July 18, 2021
4:09 pm

There have been numerous investigations into the use of the Performance Monitoring Counters (PMCs) for malware detection. Below is a quick survey of what I’ve read so far, as well as an investigation into using JTAG as an alternative access mechanism to traditional ring 0 or restricted OS mechanisms.

Webinar: Super-fast Flash Programming

Alan Sguigna

July 5, 2021
6:41 pm

100X faster than boundary scan! Watch this webinar recording of JTAG-based technologies used to do ultra-high-speed flash device programming.

Coding to the SED API: Part 5

Alan Sguigna

May 2, 2021
3:31 pm

In this installment of the Coding to the SED API series, we’ll look at the SED functions that access the OOBMSM, and use it for super-fast retrieval of hardware telemetry data.

Webinar: Embedded JTAG/boundary scan for Built-In Self Test

Alan Sguigna

April 25, 2021
12:20 pm

Attend our webinar on using JTAG as firmware for implementing boundary scan as Built-In Self Test.

The UP Squared Chronicles Episode 5: Installing and Debugging Windows 10

Alan Sguigna

April 25, 2021
12:09 pm

I hadn’t done anything with my Apollo Lake-based AAEON UP Squared board for a while. It was time to pull it down off the shelf, install Windows 10, and use SourcePoint to debug the platform.

A Trio of Webinars on x86 JTAG-based Debugging

Alan Sguigna

April 10, 2021
5:23 pm

For each of the months of January, February and March, I did a webinar on JTAG-based debugging. Since each of the video recordings are about 45 minutes long, I thought it would be helpful to point out the highlights of each, if you don’t have time to sit through the full durations. At the risk of sounding immodest, there are some real gems of information within the demos of each webinar.

Webinar: Embedded @Scale JTAG-based Debug of x86 Servers

Alan Sguigna

March 7, 2021
4:20 pm

Beginning with Microsoft Azure's Project Olympus, and now a standard within the Open Compute Project, many datacenter servers are now optionally equipped with hardware connectivity between the platform BMC and CPU scan chain. The BMC can thus act as an autonomous JTAG-based embedded out-of-band debug agent, provide low-level triage of system events, such as crashes and hangs. Other use cases, such as hardware validation, manufacturing test, and forensics telemetry are also enabled by this technology.

Using the Intel Trace Hub for at-speed printf

JTAG-based debug of AMD servers: webinar notes

[Webinar] Squeezing out more test coverage with Component Action

Performance Counters for Malware Detection: a Survey

Webinar: Super-fast Flash Programming

Coding to the SED API: Part 5

Webinar: Embedded JTAG/boundary scan for Built-In Self Test

The UP Squared Chronicles Episode 5: Installing and Debugging Windows 10

A Trio of Webinars on x86 JTAG-based Debugging

Webinar: Embedded @Scale JTAG-based Debug of x86 Servers

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