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Vivado Programming Production Challenges – Here’s a Better Way

Larry Osborn

November 17, 2021
4:37 pm

Recently as ASSET is a 3rd party tool supporter of Xilinx FPGAs for a number of applications, I was reviewing the Xilinx community seeing a lot of users trying to use Vivado and Platform Cable USB II pod for production in-system programming with less-than-optimal results or no results at all. First, Xilinx says the Platform Cable USB II with Vivado/SDK as the UI, is to be used for prototype programming and is a design tool, not a production tool.

DCI Debug on the AAEON UP Xtreme i11 board

Alan Sguigna

October 31, 2021
5:24 pm

Finally! A publicly available board with Intel Direct Connect Interface (DCI) working out of the box. With our SourcePoint JTAG-based debugger, it is now possible to explore the inner workings of low-level firmware with all the power of CPU-hardware-assisted run-control and trace features, including Intel Processor Trace and Architectural Event Trace.

Webinar: Beyond printf

Alan Sguigna

October 17, 2021
5:46 pm

In collaboration with the UEFI Forum, I’ll be presenting Beyond Printf: Real-Time UEFI Debugging on Wednesday, October 27th, 2021 at 10am CT. Register here: https://www.brighttalk.com/webcast/18206/512103 to watch the session live, and/or later view the recorded video. What powerful new debugging and trace features exist on the latest Intel silicon? Continue reading, or watch the webinar.

Using the Intel Trace Hub for at-speed printf

Alan Sguigna

September 6, 2021
5:27 pm

For debugging firmware, print statements (“printf”) are often our most powerful tool: some bugs are caused by complex sequences of events that are too long and intricate to root-cause using just breakpoints and watch windows. In this article, I write about my explorations into “at-speed printf”.

JTAG-based debug of AMD servers: webinar notes

Alan Sguigna

August 22, 2021
3:40 pm

Earlier this year, I did a webinar on using our SourcePoint JTAG-based debugger on AMD EPYC platforms. Below is the transcript of the audio, for those who prefer to read some of the material.

[Webinar] Squeezing out more test coverage with Component Action

Alan Sguigna

August 1, 2021
3:56 pm

Our upcoming webinar, to be held on Tuesday, August 31st, 2021 at 10:30am Central Time and presented by ASSET's Michael R. Johnson, will describe the Component Action methodology, provide an in-depth view of the programming model, and demonstrate examples on a live target.

Performance Counters for Malware Detection: a Survey

Alan Sguigna

July 18, 2021
4:09 pm

There have been numerous investigations into the use of the Performance Monitoring Counters (PMCs) for malware detection. Below is a quick survey of what I’ve read so far, as well as an investigation into using JTAG as an alternative access mechanism to traditional ring 0 or restricted OS mechanisms.

Webinar: Super-fast Flash Programming

Alan Sguigna

July 5, 2021
6:41 pm

100X faster than boundary scan! Watch this webinar recording of JTAG-based technologies used to do ultra-high-speed flash device programming.

Coding to the SED API: Part 5

Alan Sguigna

May 2, 2021
3:31 pm

In this installment of the Coding to the SED API series, we’ll look at the SED functions that access the OOBMSM, and use it for super-fast retrieval of hardware telemetry data.

Webinar: Embedded JTAG/boundary scan for Built-In Self Test

Alan Sguigna

April 25, 2021
12:20 pm

Attend our webinar on using JTAG as firmware for implementing boundary scan as Built-In Self Test.

Vivado Programming Production Challenges – Here’s a Better Way

DCI Debug on the AAEON UP Xtreme i11 board

Webinar: Beyond printf

Using the Intel Trace Hub for at-speed printf

JTAG-based debug of AMD servers: webinar notes

[Webinar] Squeezing out more test coverage with Component Action

Performance Counters for Malware Detection: a Survey

Webinar: Super-fast Flash Programming

Coding to the SED API: Part 5

Webinar: Embedded JTAG/boundary scan for Built-In Self Test

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