Boundary Scan Archives | Page 8 of 13

Memory Training, Testing, and Margining

Alan Sguigna

November 2, 2014
3:38 pm

What happens during DDR memory training/initialization, and how does it differ from what is needed for manufacturing testing or system marginality validation?

I2C Functional Test | 1149.1 JTAG and FPGA IP

Kent Zetterberg

September 10, 2014
11:30 am

JTAG | one TAP, many non-intrusive apps

Adam Ley

September 9, 2014
12:42 pm

The origins of JTAG are inextricably bound up with boundary scan. Yet, it provides many capabilities to many purposes. Often, as part of a point tool, whether for debug, programming, test or validation, it takes on just one capability. But, no matter the purpose, as the thread common to all, the standard Test Access Port (TAP) opens the way for many applications. In the test domain, several of these unite under the banner Non-intrusive Board Test (NBT).

DDR Testing using Spoofed Memory Reference Code – Part 2

Alan Sguigna

July 20, 2014
3:42 pm

In Part 1 of this blog, we discussed some of the limitations of ICT, boundary-scan, and conventional functional test for testing memories. This Part 2 reviews methodologies that overcome these constraints.

DDR Testing using Spoofed Memory Reference Code – Part 1

Alan Sguigna

July 13, 2014
2:55 pm

Off-the-shelf memory initialization routines typically do not provide the needed diagnostic resolution if a structural failure causes the system to “blue screen”. How can test engineers overcome this?

JTAG | IJTAG Semiconductor and Board Test Security

Al Crouch

July 1, 2014
12:36 pm

SPI Flash JTAG Programming Using a Xilinx Spartan® FPGA

Kent Zetterberg

June 10, 2014
4:10 pm

Freescale EzPort Programmer with JTAG | FPGA

Kent Zetterberg

May 8, 2014
5:05 am

Fast Flash Parallel In-System Programming | ISP | JTAG

Kent Zetterberg

April 10, 2014
12:58 pm

Serial Port Functional Test with FPGA UART IP and JTAG

Kent Zetterberg

March 11, 2014
7:00 am

Category: Boundary Scan

Memory Training, Testing, and Margining

I2C Functional Test | 1149.1 JTAG and FPGA IP

JTAG | one TAP, many non-intrusive apps

DDR Testing using Spoofed Memory Reference Code – Part 2

DDR Testing using Spoofed Memory Reference Code – Part 1

JTAG | IJTAG Semiconductor and Board Test Security

SPI Flash JTAG Programming Using a Xilinx Spartan® FPGA

Freescale EzPort Programmer with JTAG | FPGA

Fast Flash Parallel In-System Programming | ISP | JTAG

Serial Port Functional Test with FPGA UART IP and JTAG

Archives

Categories