Category: Boundary Scan

As we’ve covered in some previous blogs, the differential, AC-coupled nature of PCI Express allows this bus to be somewhat self-healing, whereby some structural defects will allow the bus to transparently run, albeit at a degraded performance. Due to this, these short-circuit and open-circuit defects may be completely masked from conventional functional test. But such defects are important to detect, because they will affect the throughput of the port. Boundary scan can be used to detect these defects, subject to the implementation of IEEE 1149.1 and IEEE 1149.6 in the chips.
In the first two parts of this multi-part blog, we reviewed different kinds of short circuit, open circuit, and stuck-at faults and how they might affect link performance. Let’s recap and rank these defects and see what we can do about them.
In my last few blogs, I’ve talked about the challenges of testing QPI, PCI Express, SATA 3, and DDR3 memory. These buses are common to many Intel Sandy Bridge and Ivy Bridge motherboard designs. Should test engineers take chances and just not test them?
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