I2C Functional Test | 1149.1 JTAG and FPGA IP

There was a time when an at-speed functional test of anything required functional operating firmware. Not so for I2C serial interfaces anymore. A new test methodology involving IEEE 1149.1 JTAG (boundary scan), an FPGA and embedded instrumentation IP means that the design and manufacturing test teams don’t have to wait around for the software department to finish the firmware for a circuit board design. They can start testing right away. Even prototypes of the design. In addition, they don’t need to spend all that time developing functional test routines that won’t provide the kind of diagnostics that’s needed anyway.

I2C_Interface_Test_with_FPGA_IP_and_JTAGThis methodology starts with structurally testing the circuit board with IEEE 1149.1 JTAG / Boundary Scan to ensure there are no assembly faults like shorts or opens on the I2C interfaces.

 This is followed by at-speed verification and testing of the interfaces with embedded instrumentation intellectual property (IP) temporarily inserted into an on-board field programmable gate array (FPGA). Once this phase in the testing is complete, the IP can be removed and the FPGA’s operational firmware inserted. The functional at-speed test IP can be re-used in other designs wherever that FPGA has been deployed.

 Essentially, what this method does is decouple the functional testing process from functional firmware development. You can take functional firmware off the list of dependencies for functional test.

 To find out more about this method and how it can save your design and manufacturing test teams a lot of time, download our new eBook,"I2C Interface Test with FPGA IP and JTAG" here.

Kent Zetterberg