Boundary Scan Archives | Page 6 of 12

Using the Intel Innovation Engine for Embedded DDR4 Memory Test

Alan Sguigna

September 7, 2015
3:28 pm

Last week, I wrote about Intel’s public announcement of the Innovation Engine (IE), an Intel architecture processor and I/O sub-system embedded into their upcoming generations of server platforms. This article describes the use of the IE for JTAG boundary-scan testing of memories.

Embedded Boundary-Scan Test

Alan Sguigna

August 2, 2015
6:09 pm

Boundary-scan test is used commonly on manufacturing lines with a “benchtop” tester, complete with cables, fixturing, hardware probes, and so on. What are the pros and cons of embedding this technology in-situ?

A new era and new insight – Real Insight

Glenn Woppman

July 13, 2015
1:21 pm

Mixing Embedded eTAPs | 1149.1, IJTAG, Software Debug

Adam Ley

April 7, 2015
4:13 pm

JTAG Diagnostics for Intel® QPI Structural Defects

Kent Zetterberg

December 16, 2014
9:22 am

Frost & Sullivan recognizes the user value of SourcePoint and ScanWorks

Glenn Woppman

December 9, 2014
11:30 am

Memory Training, Testing, and Margining

Alan Sguigna

November 2, 2014
3:38 pm

What happens during DDR memory training/initialization, and how does it differ from what is needed for manufacturing testing or system marginality validation?

I2C Functional Test | 1149.1 JTAG and FPGA IP

Kent Zetterberg

September 10, 2014
11:30 am

JTAG | one TAP, many non-intrusive apps

Adam Ley

September 9, 2014
12:42 pm

The origins of JTAG are inextricably bound up with boundary scan. Yet, it provides many capabilities to many purposes. Often, as part of a point tool, whether for debug, programming, test or validation, it takes on just one capability. But, no matter the purpose, as the thread common to all, the standard Test Access Port (TAP) opens the way for many applications. In the test domain, several of these unite under the banner Non-intrusive Board Test (NBT).

DDR Testing using Spoofed Memory Reference Code – Part 2

Alan Sguigna

July 20, 2014
3:42 pm

In Part 1 of this blog, we discussed some of the limitations of ICT, boundary-scan, and conventional functional test for testing memories. This Part 2 reviews methodologies that overcome these constraints.

Category: Boundary Scan

Using the Intel Innovation Engine for Embedded DDR4 Memory Test

Embedded Boundary-Scan Test

A new era and new insight – Real Insight

Mixing Embedded eTAPs | 1149.1, IJTAG, Software Debug

JTAG Diagnostics for Intel® QPI Structural Defects

Frost & Sullivan recognizes the user value of SourcePoint and ScanWorks

Memory Training, Testing, and Margining

I2C Functional Test | 1149.1 JTAG and FPGA IP

JTAG | one TAP, many non-intrusive apps

DDR Testing using Spoofed Memory Reference Code – Part 2

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