In Part 3 of this series, I looked at the JTAG scan path of the ASSET ScanLite demo board, and explored some of the fundamentals of IEEE 1149.1. This week, I do some fault insertion on the scan path, and see how that is detected by boundary scan.
In the last blog, I explored the JTAG scan path of the ScanLite demonstration board. In this article, I do a deeper dive into what options are available within ScanWorks to verify the scan path, and explore some of the underlying technology of IEEE 1149.1.
I’ve gotten all of my Christmas shopping done early, so I managed to make some time for exploring our ScanWorks test tool. I’m taking a “newbie approach” to using the tool, initially for hacking around with boundary-scan test. There’s some pretty cool technology here.