ASSET is pleased to host a webinar on Chiplet interconnect testing using JTAG/boundary scan, to be held on Wednesday, December 2nd at 1pm Central Standard Time. This technology session will cover:
- Use of JTAG IEEE 1149.1/1149.6 for testing of single-ended and differential die-to-die interconnects
- Wagner patterns versus alternatives for optimizing test coverage and diagnostics
- Benefits of improved device performance through the identification of structural defects.
To register, click here. Looking forward to meeting you then!