Designing with DDR memories can be challenging, and the moves from DDR3 to DDR4 and beyond don’t lessen the challenge. By now we all know that configuration of DDR memories in a board design involves dozens to hundreds of register writes to the memory controller. The memory controller registers set the timing parameters and operating mode of the DDR interface. There are two distinct types of values used in the configuration of the controller. These values can be thought of as those that are static, not subject to board, component or environmental conditions; and dynamic, specifically used to account for timing variations caused by board layout or environmental conditions.
Programming of the memory controller is influenced by several aspects of the board design. If any of these items are changed, then the memory controller settings must also change.
- Processor/memory controller used
- Number and organization of physical memory chips used
- Speed grade of the memory chips
- Operating speed of the DDR interface
- Board layout, including trace length and impedance considerations.
Static DDR Configuration Parameters
Many of the memory controller configuration parameters are static. These parameters are fixed based on the processor, memory chips, and operating speed of the DDR interface. Changes to the board layout and termination on the DDR interface don’t change the static configuration parameters. These static values are found in the memory vendor’s data sheet and are the timing values as defined by the JEDEC standard. All that is required of the user is to enter the data for the appropriate register. This is a straightforward process, however very tedious, given dealing with the register name conversion to address and working in hex.
DDR Tuning and Calibration
In addition to the static DDR parameters, some memory controllers provide settings to calibrate the operation of the memory bus to adjust for board layout variations. Each board design should determine the optimal calibration settings to improve signal integrity and reliability of the memory bus.
Common DDR Calibration parameters include:
- Write leveling
- DQS gating
- Read data eye
- Write data eye
The JEDEC standard requires that DDR3 and DDR4 memories support write leveling, but other calibration types are optional.
DDR calibration should be run against a sample of boards during the board bring up stage while the boards are running at ambient temperature. Processor vendors recommend sampling 5-10 boards and checking that the calibration results across the boards are consistent. Once consistent DDR calibration results are determined, the optimal DDR setting should be applied and the boards tested under the required environmental conditions.
The goal of write leveling is to adjust the timing of the write DQS signals relative to the DDR clock. The DDR PHY in the memory controller adds a programmable delay to the DQS signal in order to meet the timing requirement of the memory part.
The JEDEC specifications for DDR3 and DDR4 memories recommends using fly-by topology to improve signal integrity. With traditional topologies, all memory bus signals are routed to each memory chip point-to-point. With fly-by topology, the address, command, and clock signals are routed to each memory chip in series, while the DQS and data signals are routed point-to-point.
When the fly-by topology is used, the write leveling must be calibrated for each byte lane individually to ensure correct operation.
The goal of DQS gating calibration is to determine when the read DQS signal is valid. Memory operations includes periods where the DQS signal is invalid and must not be sampled to prevent incorrect behavior. The invalid states include when the read DQS signal is tri-stated or it is actively driven by the memory controller PHY. This is an optional calibration step, depending on the processor and memory controller.
Read Data Eye
The goal of read data eye calibration is to align the read DQS signal to the center of the valid read data. This is an optional calibration step, depending on the processor and memory controller.
Write Data Eye
The goal of write data eye calibration is to align the write DQS signal to the center of the valid write data. This is an optional calibration step, depending on the processor and memory controller.
Having this information is good but, what is needed are tools that address the engineering costs and tedious nature of the tuning process. The tools also need to provide extremely robust memory testing capabilities. Stressing the memory accesses is the only way to determine if the calibration is correct. You don’t want your customers to find the problem for you.
Silicon manufacturers deliver tools that provide for the initial configuration of the DDR controllers, but are they targeting your requirements, and do they fully support your testing efforts in both design and production?
That is why the silicon vendors have ecosystems of third parties that specialize in various aspects of helping their customer get to market. ASSET’S ScanWorks Processor-based Functional Test for DDR (PFTDDR) is one of those tools that address DDR tuning-to-test challenges in SoCs from Xilinx.
The tool is unique because it is architecturally specific and operates within the on-chip memory to provide a stable platform from prototype to production for dealing with DDR memories.
To find out more about cost effectively mastering your DDR tune-to test challenges, check out our new eBook, DDR Tuning and Calibration Guide on Zynq-7000, ScanWorks Processor-based Functional Test for DDR, Tune-to-Test .