Yes, we all know that that i.MX 8 SoC has been introduced and being gobbled up by the early adopters. The age of the i.MX 6 family puts this SoC squarely in the market mainstream. It's curious that when a processor or SoC moves into the mainstream, we somehow think designing with this will be easier and less perilous. After all, there are plenty of designs and software available. Yet somehow our design never goes as smoothly as planned, and there are many late nights and weekends spent learning about the nuances of the silicon as it applies to your design. Then there’s all the coding and experiments to see if all the register settings are correct and meet our expectations.
One area that you need not sweat over too much is the calibration of the DDR3 memories and MMDC controller and PHY configuration, provided you use the correct set of tools, depending on the amount of calibration measurements or register settings that are available within the SoC architecture. At first glance in the TRM there is an automated approach for DDR3 calibration within the i.MX 6, but will that provide what is needed for the environmental constraints of your design? Or provide what are the optimal settings?
The only way to be certain that the DDR3 memories and associated components are correctly calibrated for your specific design is to run a software calibration routine and get all the data. So you head back to the TRM only to find there are 125 pages dedicated to the MMDC. Ugh! There has got to be a better way. There is! And the eBook "DDR Tuning and Calibration on the NXP i.MX 6Quad" is a great place to start because it is not only about register settings, it’s also about iterative testing to ensure you have what your design requires.