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Semiconductor Test: What opportunities are created by passing the CHIPS bill?

Glenn Woppman

August 29, 2022
1:17 pm

The CHIPS Act as a byproduct will create a fantastic opportunity for high-paying semiconductor test, design-for-test and validation engineering jobs for America.

What are Chipkits?

Alan Sguigna

August 22, 2022
8:12 am

Cyber attackers use Rootkits to implant malware using Operating System internals. Bootkits are for more persistent implants, targeted toward UEFI firmware vulnerabilities. But, what if you go lower down, into the silicon? This is a Chipkit.

New Features in SourcePoint 7.12.22

Alan Sguigna

August 14, 2022
4:42 pm

Our new SourcePoint Intel release, 7.12.22, is now in production and available to all subscribers. Our most polished, fully-featured release yet, it adds the following features:

Hypervisor and OS Kernel Debug with DCI on the AAEON Whiskey Lake board

Alan Sguigna

July 17, 2022
7:09 pm

DCI debug of UEFI and hypervisor technologies with full source code.

Advanced Breakpoints for AMD Debug

Alan Sguigna

July 1, 2022
5:56 pm

It’s probably not well-known, but AMD platforms have special low-level breakpoint capabilities that aren’t available on Intel platforms. They are extremely powerful; here’s how to use them.

JTAG Debug using DCI on the AAEON UP Xtreme Whiskey Lake board

Alan Sguigna

March 27, 2022
12:13 pm

If you want to learn about UEFI, you have to be able to see the source code and debug it. Here’s how to build a debug Tianocore image on the AAEON UP Xtreme Whiskey Lake board, flash it onto the target, and use SourcePoint to debug it with Intel Direct Connect Interface (DCI).

Using JTAG for Hypervisor Debug: Part 3

Alan Sguigna

February 21, 2022
5:34 pm

Using a JTAG-based debugger to do Type 1 UEFI hypervisor debug.

SourcePoint Hobbyist Update, and Hypervisor Course Review

Alan Sguigna

February 6, 2022
3:25 pm

A status update on SourcePoint Intel JTAG debugger for individual hobbyists and researchers, and a refresher on hypervisor development.

Debugging Type 1 Hypervisors on the UP Xtreme i11 using JTAG/DCI

Alan Sguigna

November 28, 2021
1:03 pm

An example of debugging a Type 1 hypervisor using JTAG and DCI on a commercially available board.

Vivado Programming Production Challenges – Here’s a Better Way

Larry Osborn

November 17, 2021
4:37 pm

Recently as ASSET is a 3rd party tool supporter of Xilinx FPGAs for a number of applications, I was reviewing the Xilinx community seeing a lot of users trying to use Vivado and Platform Cable USB II pod for production in-system programming with less-than-optimal results or no results at all. First, Xilinx says the Platform Cable USB II with Vivado/SDK as the UI, is to be used for prototype programming and is a design tool, not a production tool.

Semiconductor Test: What opportunities are created by passing the CHIPS bill?

What are Chipkits?

New Features in SourcePoint 7.12.22

Hypervisor and OS Kernel Debug with DCI on the AAEON Whiskey Lake board

Advanced Breakpoints for AMD Debug

JTAG Debug using DCI on the AAEON UP Xtreme Whiskey Lake board

Using JTAG for Hypervisor Debug: Part 3

SourcePoint Hobbyist Update, and Hypervisor Course Review

Debugging Type 1 Hypervisors on the UP Xtreme i11 using JTAG/DCI

Vivado Programming Production Challenges – Here’s a Better Way

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