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Our chief technologist of non-intrusive board test, Adam Ley, recently published an e-Book on solving the problem of diminishing test coverage from In-Circuit Test (ICT). Whatโ€™s the key take-away from this publication?
We know from empirical evidence that a systemโ€™s operating margins are as sensitive to the chips on the board, as they are to the boardโ€™s design and manufacturing process itself. Why is this so?
In a previous blog, I described how fixed and adaptive equalization techniques are used within chips to ensure signal integrity even in adverse system conditions. Why is it important to tune these parameters within a chip?
Modern high-speed I/O equalization schemes typically include both fixed (programmable) and adaptive components to ensure signal integrity even in adverse system conditions. What tools are available to ensure that these equalization techniques are working properly on a given system?
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