Find out what the buzz was at this year’s International Test Conference (ITC). IJTAG is the answer. Read more!!
I just returned from the International Test Conference (ITC)
hosted at the Disneyland Hotel and Convention Center again this year. The show
attendance was a similar size to last year with most of the leading
design-for-test (DFT) and test engineers from the semiconductor industry plus some
test engineers from the system companies. Each year the show organizers give
the ITC a theme or tagline, but I have found that the show itself each year
generates it own theme, focus or buzz if you will. This year it was clearly
IJTAG, the IEEE p1687 standard that is close to going to ballot. Let me share
the facts that back up my point.
In our booth at ASSET, we had a Technology Demonstration of
an IJTAG flow from Synopsys’ DFTMAX (test compression IP) and Tetramax (ATPG)
through a process that produced ICL (Instrument Connectivity Language of IJTAG)
and PDL (Procedural Description Language of IJTAG) into ScanWorks’ IJTAG
Development tools to run the instrument in an FPGA (demo vehicle for SoC
application). As Robert Ruiz, Synopsys DFT Product Manager, said in our joint
customer meetings reviewing the flow “IJTAG needs an ecosystem established
so everyone in the product life-cycle can gain the benefit”, and he is
dead on with that viewpoint. So in this case Synopsys and ASSET demonstrated
putting an instrument in during the design phase, then running the instrument
in a chip, finding a failure and feeding that data back to the Synopsys
diagnostic tool to identify a stuck-at in some combinational logic. The flow is
very simple and powerful, and many customers were excited to see IJTAG come to
Mentor announced at the show that their Tessent product line
now fully supports IJTAG and all their instruments will be accessible via IJTAG
in their customers chips. They will output PDL and ICL to help seed the
ecosystem that Robert mentioned. At their booth they had very well-attended
open presentations on their IJTAG solution throughout the show. http://www.mentor.com/company/news/mentor-new-tessent-ijtag-automates-ip-test-and-debug-integration
In addition, Mentor held a “sold out” (tickets
were free from Mentor) luncheon where Steve Pateras, Mentor DFT product
manager, gave an overview of the Mentor IJTAG tools. Jeff Rearick, Technical
Editor of the IJTAG standard, gave a standard overview and update, and NXP
semiconductor presented a case study of being an early adopter of the Mentor
IJTAG tools and the value they saw.
In our booth, and jointly with Synopsys, we talked to many
customers that are beginning to implement the standard or are looking at it
very seriously. As Jeff told the luncheon audience, many people have already
used the TAP as an access mechanism to instruments, and in most of the those
cases you can just document the ICL and PDL and start using IJTAG, since simple
TAP-to-instruments connections are part of the standard.
In addition, there were sessions that included IJTAG
presentations and discussions. The IJTAG standards work has taken a long-time
and to be frank that has cost it some momentum, but this ITC was a great step
in regaining the momentum and excitement for the pending standard. ASSET is
very commitment to being one of the leaders helping develop the ecosystem for
IJTAG for the benefit of all.
For more information on IJTAG, Download a FREE IJTAG tutorial.
As the standard moves through the process I’ll blog about it
to keep you all informed.