PRBS31 and Validation of High-Speed SerDes

What’s the right dwell time, or pattern length, to consider
when checking for intersymbol interference, clock recovery, and circuit drift?

A PRBS31 pattern (pseudo-random bit sequence of length 231
– 1, or 2,147,483,647 bits) is considered the “gold standard” when it comes to stressing high-speed I/O circuits like PCI Express, 40Gbps Ethernet, and OIF/CEI
11G-SR. PRBS31 provides a most stressful environment to detect random jitter
(RJ), sinusoidal jitter (SJ), intersymbol interference (ISI), crosstalk and
other flaws – in other words, to achieve a confidence level in the operating
margins of a product.

The problem with PRBS31 is it costs too much. It usually
takes about 20 repeats of the PRBS31 pattern to meet desired confidence levels.
High-end 33GHz oscilloscopes can’t store even one pattern of that size. And
BERTs don’t work either because RJ and SJ cause pattern elements to drift
between repetitions.

Of course, there are different pattern generation and
capture algorithms, most notably the OIF-CEI
“CID Jitter Tolerance Pattern”
, which are less costly in terms of test
time. This particular implementation requires a pattern of about 21,000 bits. But
it does require resources on the IC to hold the pattern, and an application
like ScanWorks to retrieve the data through the JTAG TAP.

Signal_Integrity_ebook_w250_2To read more about alternative and better ways to check signal integrity on high-speed I/O, check out this e-Book:
Bandwidth tests reveal shrinking eye diagrams and
signal integrity problems