Adaptive Equalization – Part 2

In a previous blog, I described how fixed and adaptive
equalization techniques are used within chips to ensure signal integrity even
in adverse system conditions. Why is it important to tune these parameters
within a chip?

In my blog subtitled The
Math is in the Chip
, we saw how fixed equalization schemes like CTLE and
adaptive schemes like DFE and AGC work together to ensure high-speed serial I/O
quality and system performance. This makes the I/O more “self-healing” in a
way, because silicon and board design issues/manufacturing variances can cause
such a wide swing in a system’s operating margins. We’ve documented how margins
follow the chips in Stephanie Akimoff’s DesignCon
white paper
, and how margins are sensitive to board manufacturing variances
in our Xeon
7500 white paper

So, a well-tuned system has a good balance between the
equalization provided by the fixed and adaptive logic. This can be illustrated


But there are cases where fixed and adaptive equalization
are out of balance. In the example below, the fixed programmable settings are
doing too much work, leaving adaptive equalization very little “wiggle room” to
improve the I/O margins, resulting in potentially collapsed eyes in field


And in another example below, the fixed settings are too
conservative, making the adaptive equalization do more work. And since the adaptive
circuitry has a larger silicon footprint, we’ll draw more power on the chip:


It’s important to measure and tune both the fixed and
adaptive equalization settings prior to shipping systems into the field. And, since each system shipped has the possibility of different chips being used (e.g. different PCIe endpoints, DIMM suppliers, etc.), PVT variability due to the chips themselves, different PCB vendors' loss profiles, etc., all these should be measured and tuned for as well.