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Common SATA Signal Integrity Issues

Alan Sguigna

June 1, 2014
1:43 pm

Serial ATA (SATA)-based systems come in a wide range of topologies and trace/cable lengths. This presents signal integrity challenges due to signal loss, reflection and crosstalk; causing SATA device detection problems, lack of interoperability, slower performance, and increased radio frequency interference. What are the main issues, and how do designers mitigate them?

Embedded IJTAG | P1687 BIST | DFTMAX Synopsys | ScanWorks

Alan Sguigna

May 22, 2014
2:23 pm

The most common questions we field about the IEEE P1687 IJTAG (Internal JTAG) standard for embedded instrumentation are: “Is anyone using P1687? Does it have real and practical applications?” The answer to these questions is an emphatic YES!

Freescale EzPort Programmer with JTAG | FPGA

Kent Zetterberg

May 8, 2014
5:05 am

System Marginality Validation DDR Memory and Serial IO

Alan Sguigna

May 1, 2014
10:32 am

Bit Error Rate of Intel QuickPath Interconnect – Part 1

Alan Sguigna

April 27, 2014
4:02 pm

The required Bit Error Rate (BER) of Intel® QuickPath Interconnect (QPI) is 1 error in 10E14 bits. The BER threshold of PCI Express is 1 error in 10E12 bits. What might account for the two orders of magnitude difference?

DDR4 Memory Timing Margining

Alan Sguigna

April 20, 2014
4:54 pm

Last week we reviewed how voltage margining was performed on DDR3 and DDR4-based systems. How is timing margining done?

Fast Flash Parallel In-System Programming | ISP | JTAG

Kent Zetterberg

April 10, 2014
12:58 pm

DDR4 vs DDR3 Memory Voltage Margining

Alan Sguigna

April 7, 2014
8:38 pm

DDR4 SDRAM brings lower voltage and faster speeds. What are the implications for system marginality validation (SMV)?

What is Surprise Link Down (SLD)?

Alan Sguigna

March 30, 2014
3:42 pm

PCI-SIG specifies a bit error rate (BER) threshold of 1E-12 or better for PCI Express 3.0. What might cause this threshold to be exceeded, and what happens if it is?

The Statistical Basis of System Marginality Validation (SMV)

Alan Sguigna

March 16, 2014
4:48 pm

Determining the margins of a system requires taking a statistically large-enough data collection sample size to achieve a meaningful result. The sample size takes into account variances due to silicon process, temperature, voltage, finite test time, and a number of other factors. What is the math behind this?

Common SATA Signal Integrity Issues

Embedded IJTAG | P1687 BIST | DFTMAX Synopsys | ScanWorks

Freescale EzPort Programmer with JTAG | FPGA

System Marginality Validation DDR Memory and Serial IO

Bit Error Rate of Intel QuickPath Interconnect – Part 1

DDR4 Memory Timing Margining

Fast Flash Parallel In-System Programming | ISP | JTAG

DDR4 vs DDR3 Memory Voltage Margining

What is Surprise Link Down (SLD)?

The Statistical Basis of System Marginality Validation (SMV)

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