The Intel Cougar Point SATA bug. Adaptive equalization and power consumption. The sources of single-bit and multi-bit DDR3 and DDR4 memory errors. These are all topics which are top-of-mind for design and test engineers. And they’re key to designing and delivering high-speed designs which perform well in the field and have sufficient margin to withstand the rigors of real-world conditions.
ASSET’s new eBook, System Marginality Validation of DDR3 | DDR4 Memory and Serial I/O, describes a new software and embedded instrumentation-based methodology for validating overall system margins. This approach, System Marginality Validation, checks on the margins of a system as a whole, as opposed to simply measuring the signal integrity of one or two channels or lanes. It also easily takes into account silicon and circuit board defects and process variances, voltage, temperature, humidity and other effects, giving a level of confidence in a system’s performance and resistance to crashes, hangs, and “surprise link down” effects.
For more on the technology behind System Marginality Validation, click here.