I get excited whenever we have an opportunity to assist the defense community with engineering challenges, whether those challenges are in the form of hardware or software, design or manufacturing.
In a prior blog, I wrote about the JTAG specificationโs upcoming 30th anniversary, and reflected on how it has evolved over the years, and the powerful use cases it can be put to. This week, we look at how to secure the JTAG interface, to prevent its abuse by bad actors.
JTAG is coming up on its 30th anniversary. And some would say itโs older than that. As I prepared for doing an introductory presentation on this amazing technology, I got a chance to reflect on how useful it has become, and what the next 30 years might be like.
Do you know how it feels when you have an itch, and you just have to scratch it? Well, after an extended hiatus from writing, I felt an overwhelming compulsion to do another MinnowBoard image build with source and symbols, do some more exploring, and then blog about it.
ASSET recently released an enhanced product for testing i.MX6-based board designs using JTAG. I fired up this new tool on the Boundary Devices SABRE Lite board, with some fun and interesting results.
Eureka again! I finally figured out how to use Yocto to build a Linux kernel with all of the symbolic debug information, so that I can see all of the source code and symbols within SourcePoint.
In Part 3 of this series, I looked at the JTAG scan path of the ASSET ScanLite demo board, and explored some of the fundamentals of IEEE 1149.1. This week, I do some fault insertion on the scan path, and see how that is detected by boundary scan.
In the last blog, I explored the JTAG scan path of the ScanLite demonstration board. In this article, I do a deeper dive into what options are available within ScanWorks to verify the scan path, and explore some of the underlying technology of IEEE 1149.1.