OEMs in the telecom industry invest in verifying the performance and conformance of the high-speed interconnects off their gear. Does the same approach apply to chip-to-chip interconnects, and in other industries?
Many of us got new laptops, e-readers, tablets, and other electronics toys as gifts over the holidays. But do these machines run as fast as they’re supposed to?
I was reflecting on how much processor speeds, memory, and data transmission rates have increased over the last few decades. And yet the same old tools and techniques are often used to bring up new designs. When do you think we fall off the cliff?
I read a very interesting article recently making the case for programming PLDs and Flash Memory at In-Circuit Test (ICT). But there may be better alternatives - see what do you think...
The challenge of system debug on Intel (and other) systems can be huge. What new tricks are available for debugging system hangs, crashes, or application errors?
Ever heard the old saw about the guy (gal) that “went to a fight and a hockey game broke out”?
I’d characterize the ongoing debate on the value and longevity of In-Circuit Test (ICT) as a bit of a brawl…
Although it has been in the news for quite a while, one of the methods thought to be the way to extend Moore’s Law is finally reaching the point where it may be deployed in the near future — 3D Silicon Integration…
One of the newest IEEE Standards Committees is currently defining the P1838 3D Test Standard. The main goal of P1838 is to develop a “Per Die” Access Mechanism that becomes a “Stacked Die” Access Mechanism when the individual die are stacked into 3D silicon. Find out more…
