Solving Intel QuickPath Interconnect and DDR Margining Issues

This past week ASSET and Intel did a presentation at the Intel Developers Forum (IDF) on using ScanWorks to solve QPI and DDR3 margining problems.

Every September, Intel hosts the IDF in San Francisco, showcasing highly informative keynotes and technical sessions for the developer community. It’s an extremely well-attended conference, with upwards of 5,000 participants. This year, ASSET’s Stephanie Akimoff and Intel’s John Huie co-chaired a Hands-On Lab for users of the ScanWorks HSIO tool. The Lab, which was open to all IDF attendees, gave participants real-time experience with the tool and broadly covered such topics as how TxEq and CTLE settings affect the margined eye, the use of the Intel SPM application, and how to optimize test time.

Following the Lab, John Huie recounted some customer stories about how the ScanWorks HSIO product helped Intel’s customers overcome design signal integrity challenges. His anecdotes about customers struggling with lossy board materials (FR4), via stubs, improper grounding, noisy supply planes, and bad signal coupling were amusing and informative.

If you’d like to view the slides from the Lab, they can be found here:


Alan Sguigna