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PCB Insertion Loss and High-Speed Buses

Alan Sguigna

July 27, 2014
3:54 pm

As high-speed differential buses on today’s board designs become faster, the maximum allowable PCB insertion loss declines. What causes this effect, and how can it be mitigated?

Embedded ITP for Remote Debug

Alan Sguigna

July 24, 2014
3:30 pm

A leading server OEM is using an embedded implementation of Intel In-Target Probe (ITP) to perform at-scale debugging, without plugging in an external emulator. How does this work?

DDR Testing using Spoofed Memory Reference Code – Part 2

Alan Sguigna

July 20, 2014
3:42 pm

In Part 1 of this blog, we discussed some of the limitations of ICT, boundary-scan, and conventional functional test for testing memories. This Part 2 reviews methodologies that overcome these constraints.

Big-Endian Little-Endian | ARM Processors | SourcePoint

Larry A. Traylor

July 15, 2014
8:13 am

DDR Testing using Spoofed Memory Reference Code – Part 1

Alan Sguigna

July 13, 2014
2:55 pm

Off-the-shelf memory initialization routines typically do not provide the needed diagnostic resolution if a structural failure causes the system to “blue screen”. How can test engineers overcome this?

JTAG | IJTAG Semiconductor and Board Test Security

Al Crouch

July 1, 2014
12:36 pm

Debug of AppliedMicro’s X-Gene ARMv8 Processor

Alan Sguigna

June 29, 2014
4:24 pm

AppliedMicro has announced availability of their X-Gene Server on a Chip, with a 50% reduction in power consumption and operating costs. How do you debug a platform designed with this part?

DDR Crosstalk Analysis using Margining Technologies

Alan Sguigna

June 22, 2014
8:02 pm

In the article DDR4 Memory Timing Margining, we described more sophisticated DDR margining tests, which determine crosstalk coupling between aggressor channels, dwords (lanes 0-31), words, bytes and lanes. How can designers use these capabilities?

PCI Express 4.0, Retimers, and Trace Length

Alan Sguigna

June 15, 2014
4:39 pm

At their developers conference two weeks ago, PCI-SIG representatives talked about doubling the bandwidth of PCI Express 3.0, while still preserving channel runs of up to 20 inches, the length of the traditional server’s data path. How is this achieved?

Shorten Firmware Development Time, Use the Right Tools

Larry A. Traylor

June 13, 2014
4:19 pm

PCB Insertion Loss and High-Speed Buses

Embedded ITP for Remote Debug

DDR Testing using Spoofed Memory Reference Code – Part 2

Big-Endian Little-Endian | ARM Processors | SourcePoint

DDR Testing using Spoofed Memory Reference Code – Part 1

JTAG | IJTAG Semiconductor and Board Test Security

Debug of AppliedMicro’s X-Gene ARMv8 Processor

DDR Crosstalk Analysis using Margining Technologies

PCI Express 4.0, Retimers, and Trace Length

Shorten Firmware Development Time, Use the Right Tools

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