Blog

Open Compute Project, and Containers vs VMs

Alan Sguigna

October 2, 2016
3:46 pm

ASSET joined the Open Compute Project (OCP) earlier this year, and we attended our first Engineering Workshop in Dallas last week. The theme of this session was the OCP Telco Project. What did we learn?

Testing Memories without BIOS on the Latest Intel Platforms

Larry Osborn

September 27, 2016
9:20 am

2016 UEFI Forum Plugfest – Seattle, WA

Alan Sguigna

September 25, 2016
4:09 pm

ASSET (yours truly) attended the September 2016 Plugfest at the UEFI Forum in Seattle, WA. Was it worthwhile?

NBT at the BTW

Alan Sguigna

September 18, 2016
4:12 pm

ASSET’s Michael Johnson presented an update on Non-intrusive Board Test (NBT) at the 13th Annual Board Test Workshop (BTW) in Fort Collins, CO this past week. The overall question posed at the Workshop was, “Is Board Test Losing Relevance”?

Debugging platform issues with Intel CScripts

Alan Sguigna

September 11, 2016
3:08 pm

How useful are the Intel Customer Scripts (“CScripts”) for debugging system issues?

Boundary-Scan Test on the TI MSP430

Alan Sguigna

September 5, 2016
1:53 pm

The MSP430 is a mixed-signal microcontroller family from Texas Instruments. Built around a 16-bit CPU, the MSP430 is designed for low cost, low power consumption embedded applications. But, does it support boundary scan for board test purposes?

Dumping Intel MSRs from Crashed Systems Remotely using Embedded ITP

Alan Sguigna

August 28, 2016
4:02 pm

When an x86 system has crashed, gathering forensics data to help diagnose root-cause of the failure is a top priority. But, how is this done if the system has crashed, and OS/BIOS-based application programs cannot access the platform?

Using Boundary-Scan Test at Debug & Repair Stations

Alan Sguigna

August 14, 2016
3:06 pm

Is it possible to use JTAG at debug & repair depots to reduce the cost of diagnosing bad boards?

The Third Type of JTAG Access on Intel-based Designs

Alan Sguigna

July 31, 2016
4:22 pm

In my last blog, I introduced the three types of JTAG access for debug applications. This article delves into the third type, Embedded ITP.

The Three Types of JTAG Access on Intel-based Designs

Alan Sguigna

July 24, 2016
5:02 pm

Pop quiz: there are three main mechanisms to access debug embedded instrumentation within Intel silicon. What are they?

Open Compute Project, and Containers vs VMs

Testing Memories without BIOS on the Latest Intel Platforms

2016 UEFI Forum Plugfest – Seattle, WA

NBT at the BTW

Debugging platform issues with Intel CScripts

Boundary-Scan Test on the TI MSP430

Dumping Intel MSRs from Crashed Systems Remotely using Embedded ITP

Using Boundary-Scan Test at Debug & Repair Stations

The Third Type of JTAG Access on Intel-based Designs

The Three Types of JTAG Access on Intel-based Designs

Archives

Categories