Category: High-Speed I/O

System Marginality Validation DDR Memory and Serial IO

Alan Sguigna

May 1, 2014
10:32 am

Bit Error Rate of Intel QuickPath Interconnect – Part 1

Alan Sguigna

April 27, 2014
4:02 pm

The required Bit Error Rate (BER) of Intel® QuickPath Interconnect (QPI) is 1 error in 10E14 bits. The BER threshold of PCI Express is 1 error in 10E12 bits. What might account for the two orders of magnitude difference?

DDR4 Memory Timing Margining

Alan Sguigna

April 20, 2014
4:54 pm

Last week we reviewed how voltage margining was performed on DDR3 and DDR4-based systems. How is timing margining done?

DDR4 vs DDR3 Memory Voltage Margining

Alan Sguigna

April 7, 2014
8:38 pm

DDR4 SDRAM brings lower voltage and faster speeds. What are the implications for system marginality validation (SMV)?

What is Surprise Link Down (SLD)?

Alan Sguigna

March 30, 2014
3:42 pm

PCI-SIG specifies a bit error rate (BER) threshold of 1E-12 or better for PCI Express 3.0. What might cause this threshold to be exceeded, and what happens if it is?

The Statistical Basis of System Marginality Validation (SMV)

Alan Sguigna

March 16, 2014
4:48 pm

Determining the margins of a system requires taking a statistically large-enough data collection sample size to achieve a meaningful result. The sample size takes into account variances due to silicon process, temperature, voltage, finite test time, and a number of other factors. What is the math behind this?

What is Board Bring-Up – Part 2

Alan Sguigna

March 9, 2014
4:09 pm

We know that the board bring-up process can be extremely challenging on today’s complex, high-speed designs. How do we get the iterative validation, test and debug steps off of the critical path of new product introduction?

Structural Defects on Intel QuickPath Interconnect – Part 2

Alan Sguigna

March 2, 2014
1:24 pm

Suppose there’s a hidden short-circuit on an Intel QPI net under the CPU socket – what’s the customer going to see?

Structural Defects on Intel QuickPath Interconnect

Alan Sguigna

February 16, 2014
11:37 am

A customer shared some empirical results from boundary-scan testing of the Intel QuickPath Interconnect (QPI) nets on their design. These nets cannot be covered using In-Circuit Test (ICT), and some short-circuit and open-circuit defects defy detection using conventional functional test. What did they find?

Signal Integrity Validation (SIV) versus System Marginality Validation (SMV) – Part 3

Alan Sguigna

February 2, 2014
5:26 pm

In previous blogs, we contrasted the use of oscilloscopes to perform signal integrity validation (SIV) against silicon embedded instruments for system marginality validation (SMV). Why is SMV superior?

Category: High-Speed I/O

System Marginality Validation DDR Memory and Serial IO

Bit Error Rate of Intel QuickPath Interconnect – Part 1

DDR4 Memory Timing Margining

DDR4 vs DDR3 Memory Voltage Margining

What is Surprise Link Down (SLD)?

The Statistical Basis of System Marginality Validation (SMV)

What is Board Bring-Up – Part 2

Structural Defects on Intel QuickPath Interconnect – Part 2

Structural Defects on Intel QuickPath Interconnect

Signal Integrity Validation (SIV) versus System Marginality Validation (SMV) – Part 3

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