Category: High-Speed I/O

The origins of JTAG are inextricably bound up with boundary scan. Yet, it provides many capabilities to many purposes. Often, as part of a point tool, whether for debug, programming, test or validation, it takes on just one capability. But, no matter the purpose, as the thread common to all, the standard Test Access Port (TAP) opens the way for many applications. In the test domain, several of these unite under the banner Non-intrusive Board Test (NBT).
In the previous blog on PCB Insertion Loss and High-Speed Buses, we described how this loss increases with greater link speed. Designing for higher link speeds may, as a consequence, drive up PCB cost. This blog explains some techniques to mitigate this cost increase.
As high-speed differential buses on today’s board designs become faster, the maximum allowable PCB insertion loss declines. What causes this effect, and how can it be mitigated?
In the article DDR4 Memory Timing Margining, we described more sophisticated DDR margining tests, which determine crosstalk coupling between aggressor channels, dwords (lanes 0-31), words, bytes and lanes. How can designers use these capabilities?
At their developers conference two weeks ago, PCI-SIG representatives talked about doubling the bandwidth of PCI Express 3.0, while still preserving channel runs of up to 20 inches, the length of the traditional server’s data path. How is this achieved?
In a previous blog, we touched on some of the key attributes of Intel QuickPath Interconnect versus PCI Express Gen3, to explain why the acceptable bit error rate threshold of Intel QPI is two orders of magnitude lower. This article elaborates on how some of the key design features of QPI contribute to this more stringent requirement.
Serial ATA (SATA)-based systems come in a wide range of topologies and trace/cable lengths. This presents signal integrity challenges due to signal loss, reflection and crosstalk; causing SATA device detection problems, lack of interoperability, slower performance, and increased radio frequency interference. What are the main issues, and how do designers mitigate them?