Category: High-Speed I/O

Back a few years ago, engineers used expensive high-end oscilloscopes to perform signal integrity validation (SIV) on their designs, and considered that adequate in determining the success of a design. But with today’s products, process and parameter variations occur that require system marginality validation (SMV) to be done by less expensive software-based tools, to determine if a design is ready for high volume production.
In previous blogs we covered the kind of defects that might exist on high-speed serial I/O and their associated impacts on system performance and stability. A similar analysis on DDR SDRAM yields some interesting findings.
In the first two parts of this multi-part blog, we reviewed different kinds of short circuit, open circuit, and stuck-at faults and how they might affect link performance. Let’s recap and rank these defects and see what we can do about them.
Shorts and open circuits on high-speed serdes buses, such as PCI Express, may have subtle and difficult-to-diagnose effects on system performance. In other words, you might not know about them until customers start complaining and you get warranty returns. What kind of effects are these, and how are they prevented?
One of the biggest design challenges today revolves around maintaining signal integrity in the presence of power and ground rail fluctuations due to simultaneously switching signals. This is particularly true for DDR4 memory.
In early 2011, Intel discovered a design issue on their Cougar Point chipset, and took an approximately $700 million charge against earnings to repair and replace affected parts and systems. What may have been the root cause of this, and how may it have been prevented?