Signal Integrity Validation (SIV) versus System Marginality Validation (SMV)

Back a few years ago, engineers used expensive high-end
oscilloscopes to perform signal integrity validation (SIV) on their designs,
and considered that adequate in determining the success of a design. But with
today’s products, process and parameter variations occur that require system
marginality validation (SMV) to be done by less expensive software-based tools,
to determine if a design is ready for high volume production.

Firstly, some definitions: SIV uses oscilloscope
measurements of select voltage and timing parameters across certain
process/voltage/temperature (PVT) corner conditions and interface
configurations. The intent of SIV is to ascertain transmitter and link robustness
via oscilloscope waveform captures.

SMV, on the other hand, uses embedded instrumentation within
silicon to perform system level margining of I/O buffer control knobs such as
VREF, buffer strength, slew rate, and timing controls, with PVT and interface
configuration variability “baked in” to an eye mask that defines an acceptable
margin.  SMV proves in the entire system
robustness, including transmitter, receiver, and interconnect link.

The problem with SIV is that it is expensive, difficult, and
slow. If you want a chuckle, watch this YouTube video
on the world’s most expensive unboxing of a $140,000 Agilent DSA91304A 13GHz
oscilloscope. And if you’re feeling really rich, check out this EUR 228,062 (a
whopping $300,000 USD by today’s exchange rate) Agilent DSOX93204A Infiniium 33GHz oscilloscope, which
you’ll need to do SIV on fast buses such as PCI Express Gen3.

Worlds most expensive unboxing

And, of course, probe heads and amplifiers aren’t cheap
either. It takes weeks to set up access to and attach the heads – and you can
only do that on early prototypes, because you don’t want too many vias on the
board messing up your signal integrity in production designs. Finally, an
oscilloscope only has a limited number of channels, which means you only
measure maybe the shortest and longest traces – there’s no way to know if, for
example, one of the lanes you don’t measure (like the one that, unbeknownst to
you, is routed near some voltage regulator noise) actually has the worst
margins, which may be responsible for intermittent system crashes.

So SMV came along to address these deficiencies. With
software-based tools that see what the silicon sees, you can margin the entire
system – Tx, Rx and interconnect. There’s no access to worry about and no
soldering to do. You can run SMV multiple times, across multiple systems, with
multiple third-party add-in cards and DIMMs – to get a high level of confidence
in your designs across a wide spectrum of possible defects and variances that
can raise their ugly heads once the system is in the field. This is important
because margins can vary statistically and substantially, from run to run, due
to variances as described in these white papers: Margins (Eye Diagrams) Follow the Silicon, and How to avoid poor serdes performance caused by circuit board
manufacturing variances
. And you can do all of this at a tiny fraction of
the cost of an oscilloscope.

So don’t get us wrong; an oscilloscope is still needed, at
least in the early stages of product development, for compliance testing and for SIV. But
SMV is the way to go to determine how much margin is in the design.