Structural Defects on High-Speed Serial I/O – Part 2

In my previous blog, we reviewed the effects of a missing capacitor and a short to ground on the performance of high-speed serial buses. What other kinds of defects should be considered, and what can we do about them?


In Structural Defects on High-Speed Serial I/O – Part 1, we saw that certain short circuits and open circuits can have either subtle or dramatic effects on buses. These can range from higher bit error rates and slower system performance due to link re-initializations and packet re-transmissions, to outright lane drop-outs (either intermittent or permanent).

These shorts and opens can be difficult to replicate in real-life experiments. In an experiment, an open simulated by pulling a jumper is an imperfect representation of what on a circuit board might be a missing ball, solder void or head-in-pillow defect. And a short-circuit derived by closing a jumper isn’t the same as excess solder bridging two balls. Experiments will often result in catastrophic bus failures; high-speed buses aren’t intended to survive these types of induced failures. But real-life opens may still permit a level of coupling on the nets, so the bus survives. And the same thing applies to shorts: the rejection of common mode noise may still allow the bus to run, albeit at a reduced level of performance.

Another example that describes this in more detail is as follows:

A SHORT CIRCUIT: Tx1- to Tx2+

High Speed IO defects graphics Part 2
In this example, the negative leg of a transmit lane (Tx1-) is shorted to the positive leg of an adjacent transmit lane (Tx2+). But as with our example from Part 1 of this blog, the receiver operates by rejecting common mode noise, and energy from Tx2+ is already coupled to both Tx1+ and Tx1-, so some of the additional coupling energy will still be rejected. So, again, the bus may continue to operate, but its performance will be impaired. The degree of impairment due to the enhanced bit error rate will determine if the bus simply undergoes numerous packet re-transmissions and PHY layer re-initializations, impacting throughput; or if it reduces in link width and/or speed, and whether such reduction is intermittent or permanent.

In a future blog I’ll describe what technologies can be used to detect the universe of defects on high-speed I/O. In the meantime, you might enjoy a white paper on performance degradations on DDR3, PCI Express, Intel QPI, USB3 and others: Bandwidth Tests Reveal Shrinking Eye Diagrams and Signal Integrity Problems.

Alan Sguigna