One of the most frequently downloaded resources on the ASSET web site is the tutorial on IEEE Std.1149.7, and with good reason. This complementary superset of the original IEEE Std 1149.1 (JTAG) enhances functionality of the Test Access Port, extends acces to multiple cores on SOC or multiple die in SIP or POP, and paves the way for use of JTAG in applications where it may not have previously been considerd.
The author of the tutorial is Adam Ley, Chief Technologiest at ASSET InterTech. Adam served as the chief author of the draft standard. Retrieve the tutorial from http://www.asset-intertech.com/Products/IJTAG-Test/IJTAG-Test-Software/IEEE-1149-7-Embedded-Tutorial