High-Speed I/O Archives | Page 7 of 10

Is there a market for on-chip instrumentation?

Alan Sguigna

September 3, 2012
1:42 pm

Brian Bailey, editor of EETimes’ EDA Designline, recently penned a blog questioning the ubiquity and value of embedded instrumentation within chips. It’s a fascinating and timely read, and I’d like to put my two cents worth in…

Testing Intel QuickPath Interconnect

Alan Sguigna

August 26, 2012
3:11 pm

Last week I published a blog on detecting defects on PCI Express. Does Intel QuickPath Interconnect (QPI) differ in any way?

Testing PCI Express

Alan Sguigna

August 16, 2012
8:16 pm

PCI Express (PCIe) buses, in particularly Gen3, are susceptible to defects which may be masked from conventional test. What are these defects and how are they detected?

Testing DDR3 and DDR4 memory – Part 2

Alan Sguigna

August 3, 2012
4:52 pm

In my last Blog, I wrote about the iNEMI report on how testing memories is one of the top three problems engineers face today. Why is memory test so important?

How to test DDR3, DDR4 and other memory buses is top-of-mind for many engineers. And rightfully so.

Alan Sguigna

July 25, 2012
2:55 pm

Testing high-speed memories soldered to a circuit board is as elusive as it is critical for overall system performance. Testing DDR3 and DDR4 memory buses can be particularly tricky, given the fact that DDR is so fast and that the bus carries the clock and data on both the rising and falling edges of the signal. Sorting all of that out and making sure it stays sorted out over the life cycle of a system can be a daunting challenge.

Embedded Run-Control for Debug and Test

Alan Sguigna

June 20, 2012
8:40 pm

Embedded run-control (aka on-chip debug, or processor debug port control) has numerous benefits in the areas of test and debug, for Design Engineering, Manufacturing Test Engineering, and Field Service. What are they?

Pollution, Power Margins, and SerDes Problems

Alan Sguigna

May 20, 2012
8:59 pm

PCI Express Loopback and PCI-SIG

Eric Johnson

April 18, 2012
2:01 pm

Increasing densities and shrinking form factors

Alan Sguigna

April 15, 2012
6:09 pm

Isn’t it a great time to be a board designer? Compared to twelve years ago, the average number of nets has gone from 1,544 to 2,832; the number of pin-to-pin connections has increased from 7,661 to 13,573; the number of components has grown from 1,120 to 3,518; and many other challenges to the job have arisen.

When Gigabit Ethernet isn’t fast enough

Alan Sguigna

March 25, 2012
2:43 pm

My neighbor’s son ripped out all the Cat 5e cable in his house and replaced it with Cat 6 cable. Why did he do that?

Category: High-Speed I/O

Is there a market for on-chip instrumentation?

Testing Intel QuickPath Interconnect

Testing PCI Express

Testing DDR3 and DDR4 memory – Part 2

How to test DDR3, DDR4 and other memory buses is top-of-mind for many engineers. And rightfully so.

Embedded Run-Control for Debug and Test

Pollution, Power Margins, and SerDes Problems

PCI Express Loopback and PCI-SIG

Increasing densities and shrinking form factors

When Gigabit Ethernet isn’t fast enough

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