Category: High-Speed I/O

Brian Bailey, editor of EETimes’ EDA Designline, recently penned a blog questioning the ubiquity and value of embedded instrumentation within chips. It’s a fascinating and timely read, and I’d like to put my two cents worth in…
PCI Express (PCIe) buses, in particularly Gen3, are susceptible to defects which may be masked from conventional test. What are these defects and how are they detected?
Testing high-speed memories soldered to a circuit board is as elusive as it is critical for overall system performance. Testing DDR3 and DDR4 memory buses can be particularly tricky, given the fact that DDR is so fast and that the bus carries the clock and data on both the rising and falling edges of the signal. Sorting all of that out and making sure it stays sorted out over the life cycle of a system can be a daunting challenge.
Embedded run-control (aka on-chip debug, or processor debug port control) has numerous benefits in the areas of test and debug, for Design Engineering, Manufacturing Test Engineering, and Field Service. What are they?
Isn’t it a great time to be a board designer? Compared to twelve years ago, the average number of nets has gone from 1,544 to 2,832; the number of pin-to-pin connections has increased from 7,661 to 13,573; the number of components has grown from 1,120 to 3,518; and many other challenges to the job have arisen.