Pollution, Power Margins, and SerDes Problems

In addition to board design/layout issues, manufacturing defects and variances, other factors such as pollution and power marginalities can affect a design’s signal integrity and subsequent performance.

In my March blog on High-Speed I/O Design Guidelines, I covered some of the key design and layout criteria necessary to ensure bus performance and reduce SerDes problems. And in a previous article within Connect, Arden Bjerkeli described process and production variances such as interconnect stripline dimensions, trace surface roughness, head-in-pillow defects and others, and their effects on signal integrity.

And just this past week, a customer described to me how they lost a substantial part of their margin on a PCI Express Gen3 lane because of an ECO (Engineering Change Order) done on a part that wasn’t even related to the PCIe connections. Their theory is that the new part drew slightly more power, “drooping” the supply to the PCIe chips and changing the size and shape of the eye diagram.

Even atmospheric pollution may play a role. Some time ago, a SerDes engineer described to me an experiment whereby increased insertion losses on high-speed buses were found to be a result of sulfur contamination on the outer surfaces of the stripline conductors. Some experiments have been done on this subject, most notably by National Semiconductor and the Helsinki University of Technology: Effects of the Solder Oxide Layer on High Frequency Signal Propagation in Pb-Free Interconnections as well as by Intel: Intel IBIST, the full vision realized (available at www.ieeexplore.org) but empirical evidence of these kinds of effects is still in short supply. In one experiment conducted by ASSET, it was in fact found that amounts of margin, bus training values, and margin lane failures all followed the batch of devices attached to the bus.

This is probably why OEM Failure Analysis engineers are finding more and more signal integrity issues with products returned from the field. Reduced margins and higher bus bit error rates are, of course, almost impossible to detect with traditional field tests and system diagnostics.