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This article describes using JTAG in combination with Intel Trace features, specifically Last Branch Record (LBR) trace, to research the internals of System Management Mode (SMM).
In part 1 of my explorations into Hypervisor-Managed Linear Address Translation (HLAT), I installed a Canary build on my AAEON UP Xtreme i12 Alder Lake board, and booted to the Windows desktop to see the VMCS field indicating that HLAT was enabled. This time, I isolated some of the code that actually turns it on.
Our goal is to enable FPGA Designers to design better and faster with Fast Flash Programming โ€“ no matter what FPGA devices theyโ€™re working on. We have extended the list of devices that we cover from FPGA vendors such as Intel (formerly Altera), AMD (formerly Xilinx), and Microchip (formerly Actel), and the list continues to grow!
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