Software Debug and Trace Archives | Page 4 of 19

Coding to the SED API: Part 4

Alan Sguigna

October 18, 2020
4:52 pm

In Part 3 of this series, we did a code review of “ltloop”, a utility firmware application that uses the BMC to do out-of-band stress tests of PCI Express ports. In this article, we begin to examine a more general-purpose application that uses JTAG to extract register, memory and IO contents of the target. This On-Target Diagnostic (OTD), called “libtest”, is used by ASSET to test the functionality of run-control on new targets.

Coding to the SED API: Part 3

Alan Sguigna

September 20, 2020
7:56 pm

In the last article on this topic, we did a dive into the main routine of the lt_loop JTAG-based On-Target Diagnostic, seeing the overall flow of the program. In this article, we’ll look at the routine that does the heavy lifting for retraining the PCI Express link and checking for errors.

Coding to the SED API: Part 2

Alan Sguigna

September 7, 2020
3:35 pm

In my previous blog, I did a walkthrough of the source code for main() within the ltloop JTAG-based on-target diagnostic. This article covers main() in more detail, and provides insight into some of the operations of the utility functions and data structures.

Coding to the SED API: Part 1

Alan Sguigna

August 30, 2020
4:11 pm

In my UEFI Forum webinar, I demonstrated a utility function for stressing PCI Express ports at-scale using JTAG. Let’s walk through the source code and see how it works under the hood.

Debugging Intel CATERR using Embedded ITP

Alan Sguigna

July 26, 2020
8:44 pm

In my webinar with the UEFI Forum, I demonstrated some of the utility of using JTAG functionality within BMCs to perform out-of-band debug. This is a tutorial on the coding practices to use the SED API.

PCI Express LTSSM stress using BMC-based Embedded JTAG/ITP

Alan Sguigna

July 19, 2020
4:27 pm

This past week, I did a webinar in collaboration with the UEFI Forum on JTAG-based UEFI Debug and Trace. This reviewed some of the often-used tools for low-level triage of difficult-to-diagnose, intermittent bugs. Near the end, I demonstrated the usage of technology running directly down on a BMC to perform low-level functions not achievable with firmware or OS-based applications.

Webinar on JTAG-based UEFI Debug & Trace

Alan Sguigna

June 24, 2020
2:23 pm

ASSET will be presenting JTAG-based UEFI Debug & Trace at the UEFI Forum’s 2020 Virtual Plugfest, on July 14th.

The UP Squared Chronicles Episode 2: Building the UEFI Image

Alan Sguigna

June 7, 2020
5:55 pm

In Episode 1 of the UP Squared Chronicles, I used my DediProg SF100 to flash a debug image equipped with source and symbols onto the UP Squared board. This week, I describe the build process.

More Skylake Server CScripts Explorations

Alan Sguigna

May 31, 2020
1:18 pm

In Running Intel CScripts on Skylake servers, I gave a brief introduction to the Intel Customer Scripts (CScripts), and showed how to run them with SourcePoint. Today, I do a deeper dive.

Open Source Firmware explorations using DCI on the AAEON UP Squared board

Alan Sguigna

May 16, 2020
4:23 pm

As you may have seen from my last blog, my old favorite open-source platform, the MinnowBoard, has been declared End-of-Life. So how am I to satisfy my innate need to explore the low-level interfaces between silicon, hardware and firmware? I may have found a new open source firmware board that meets my needs.

Category: Software Debug and Trace

Coding to the SED API: Part 4

Coding to the SED API: Part 3

Coding to the SED API: Part 2

Coding to the SED API: Part 1

Debugging Intel CATERR using Embedded ITP

PCI Express LTSSM stress using BMC-based Embedded JTAG/ITP

Webinar on JTAG-based UEFI Debug & Trace

The UP Squared Chronicles Episode 2: Building the UEFI Image

More Skylake Server CScripts Explorations

Open Source Firmware explorations using DCI on the AAEON UP Squared board

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