Category: Non-intrusive Board Test (NBT)

We know that the board bring-up process can be extremely challenging on today’s complex, high-speed designs. How do we get the iterative validation, test and debug steps off of the critical path of new product introduction?
A customer shared some empirical results from boundary-scan testing of the Intel QuickPath Interconnect (QPI) nets on their design. These nets cannot be covered using In-Circuit Test (ICT), and some short-circuit and open-circuit defects defy detection using conventional functional test. What did they find?
A Case Study showed that 50% of circuit boards that tested as “dead” in manufacturing production actually have defects on their memory buses. What categories of memory interconnect defects cause a dead board?
To quote Ransom Stephens in the DesignCon Community Blog, “BIST (Built-In System Test), is an acronym that would keep executives at test-and-measurement companies awake at night, if they knew what it meant.” What’s he talking about?
As we’ve covered in some previous blogs, the differential, AC-coupled nature of PCI Express allows this bus to be somewhat self-healing, whereby some structural defects will allow the bus to transparently run, albeit at a degraded performance. Due to this, these short-circuit and open-circuit defects may be completely masked from conventional functional test. But such defects are important to detect, because they will affect the throughput of the port. Boundary scan can be used to detect these defects, subject to the implementation of IEEE 1149.1 and IEEE 1149.6 in the chips.
Last month, we saw how defects on memory data lines can cause a system to fail, and yet escape detection by the system boot loader or BIOS. Let’s examine this in more technical detail.