Category: Non-intrusive Board Test (NBT)

Shorts and open circuits on high-speed serdes buses, such as PCI Express, may have subtle and difficult-to-diagnose effects on system performance. In other words, you might not know about them until customers start complaining and you get warranty returns. What kind of effects are these, and how are they prevented?
Our chief technologist of non-intrusive board test, Adam Ley, recently published an e-Book on solving the problem of diminishing test coverage from In-Circuit Test (ICT). What’s the key take-away from this publication?
In a previous blog, I described how fixed and adaptive equalization techniques are used within chips to ensure signal integrity even in adverse system conditions. Why is it important to tune these parameters within a chip?
Ever wonder if a stray cosmic ray or alpha particle might double your bank account, due to an undetected RAM error?
In my last few blogs, I’ve talked about the challenges of testing QPI, PCI Express, SATA 3, and DDR3 memory. These buses are common to many Intel Sandy Bridge and Ivy Bridge motherboard designs. Should test engineers take chances and just not test them?
When you come right down to it, we spend too many days/nights, weeks and weekends writing code for device configuration, production test and system test. The question I’d like to raise is: What is the value of these home grown tests? Do they provide intrinsic and tangible value to your end customer?
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