Will BIST Kill T&M?

To quote Ransom Stephens in the DesignCon Community Blog, “BIST (Built-In System Test), is an acronym
that would keep executives at test-and-measurement companies awake at night, if
they knew what it meant.”
  What’s he
talking about?

In his blog, Ransom describes the use of BIST for accessing the
“real eye diagram” (and thus the true margin of the bus) as seen within the
chip. You want to see what the silicon sees, because an external probe
introduces ISI (inter-symbol interference), multi-path interference, and
multiple internal reflections due to the frequency response of connectors,
traces, cables, backplanes, and all other introduced points of discontinuity. Sure,
you can try to de-embed all that noise mathematically to obtain the true
signal, but, in his words, “Suspicious? I
hope so… In principle, it's possible to de-embed all the way into the chip
if the S-parameters are known, in practice, you'd need superconducting test

Further, Ransom describes an experiment conducted by Eric
Kvamme of LSI, where BIST was used to display bathtub plots of a 25Gbit/s part
down to a bit error ratio of 1E-15. That couldn't have been performed without
BIST. In other words, forget about using an oscilloscope.

Within ASSET, we use BIST in a more generic sense, by
referring to “embedded instruments”. These embedded instruments can be used for
test, but also for design validation and for platform debug as well. A good
example of an embedded instrument for the purpose of board test is IEEE 1149.1,
aka known as boundary scan. An embedded instrument used for the purpose
of design validation is Intel®
. And an embedded instrument used for the purposes of platform debug
is run-control (aka debug-port control), as is used in the Arium product.

The traditional T&M companies have good reasons to lay
awake at night.