Testing System Clocks with an FPGA
and JTAG | Boundary Scan

By Kent Zetterberg Testing-System-Clocks-FPGA-JTAG-Boundary Scan_w250

We live in a synchronized world! Devices are our daily bread-and-butter: like smartphones, tablets, laptops, desktops, servers, gaming consoles, music players and TV sets. All are all highly complex. All contain  printed circuit boards (PCB) with one or more microprocessors, chipsets, FPGAs, ASICs, DDR memory, flash memory and on and on the list goes. What all of these devices have in common are clock distribution networks that allow all of these devices and their functions to be synchronized at speeds beyond imagination. Try to envision one thousand million sine waves flashing by your eyeballs every second. And some systems run even faster! What happens if one of those clocks isn’t working? You’ll hear:

“My boards won’t boot.”

“The functional test doesn’t work.”

“Fault-finding is difficult without a working system.”

By testing the clocks early in the test sequence, the engineer reduces the time needed to bring up prototypes and he allows additional time for more robust functional testing and fault finding during manufacturing. And it’s all based on non-intrusive embedded instrumentation.

One of our recent eBooks explains how system clocks on PCBs can be quickly tested with simple, cost-effective, yet powerful and precise methods without expensive capital equipment test systems on the production line.

Have a look at our new eBook.