As described in earlier blogs, the new Intel Innovation Engine (IE) makes an ideal host for validation, debug, trace and test applications on Intel platforms. This article details the implementation of a JTAG execution engine on the IE for the purposes of printed circuit board structural and functional testing.
Last week, I wrote about Intel’s public announcement of the Innovation Engine (IE), an Intel architecture processor and I/O sub-system embedded into their upcoming generations of server platforms. This article describes the use of the IE for JTAG boundary-scan testing of memories.
Just this past week, Intel announced the Innovation Engine, a small Intel architecture processor and I/O sub-system embedded into their upcoming generations of server platforms. What is its purpose, and what new applications can run on it?
Boundary-scan test is used commonly on manufacturing lines with a “benchtop” tester, complete with cables, fixturing, hardware probes, and so on. What are the pros and cons of embedding this technology in-situ?
Let’s say you wanted to debug a CATERR on an Intel x86-based system out in the field. And let’s say that the CATERR only happened in a given datacenter once a week. An embedded implementation of the In-Target Probe (ITP) would help.
Highly Accelerated Life Testing (HALT) and Highly Accelerated Stress Screening (HASS) are often used to detect faults in electronic systems, testing the extremes and determining the outer limits of system margins. All hardware components and systems will eventually fail under environmental stress. But can this technique be used to improve software reliability as well?